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Analysis of problems in PCB design (26-40)
Posted:05:26 PM October 18, 2018 writer: G

The reason for separating the digital/analog ground is because the digital circuit generates noise at the power supply and ground when switching between high and low potentials, and the magnitude of the noise is related to the speed and current of the signal. If the ground plane is not divided and the noise generated by the digital area circuit is large and the circuits of the analog area are very close, the analog signal will still be disturbed by the ground noise even if the digital-to-analog signals do not cross. That is to say, the method of digitally undivided can only be used when the analog circuit area is far away from the digital circuit area where large noise is generated.

27. Another method is to ensure that the digital/analog separate layout, and the digital/analog signal traces do not cross each other, the entire PCB board is not divided, and the digital/analog ground is connected to the ground plane. What is the truth?

The requirement that the digital-to-analog signal traces cannot be crossed is because the return current path of the digital signal with a slightly faster speed will flow back to the source of the digital signal as far as possible below the trace, if the digital-to-analog signal is crossed. , the noise generated by the return current will appear in the analog circuit area.

28. How to consider impedance matching when designing high-speed PCB design schematics?

Impedance matching is one of the design elements when designing high speed PCB circuits. The impedance value has an absolute relationship with the routing method, such as walking on the surface (microstrip) or inner layer (stripline/double stripline), the distance from the reference layer (power layer or ground layer), the trace width, the PCB material, etc. Will affect the characteristic impedance value of the trace. That is to say, the impedance value can be determined after wiring. General simulation software can not consider some non-continuous wiring conditions due to the limitation of the line model or the mathematical algorithm used. At this time, only some terminators, such as series resistors, can be reserved on the schematic. Moderate the effect of discontinuity in the trace impedance. The only way to solve the problem is to pay attention to avoiding impedance discontinuities.

29. Where can I provide a more accurate IBIS model library?

The accuracy of the IBIS model directly affects the results of the simulation. Basically, IBIS can be regarded as the electrical characteristics of the actual chip I/O buffer equivalent circuit. It can be converted from SPICE model (can also be measured, but more limited), while SPICE data and chip manufacturing have absolute Relationship, so the same device is provided by different chip manufacturers, the SPICE data is different, and the data in the converted IBIS model will also be different. That is to say, if the A manufacturer's devices are used, only they have the ability to provide accurate model data for their devices, because no one else knows better than them what process their devices are made of. If the IBIS provided by the manufacturer is inaccurate, it is the fundamental solution to continuously ask the manufacturer to improve.

30. When designing high-speed PCBs, should designers consider the rules of EMC and EMI from those aspects?

In general, EMI/EMC design needs to consider both radiated and conducted. The former belongs to the higher frequency part (>30MHz) and the latter is the lower frequency part (<30MHz). Pay attention only to the high frequency and ignore the low frequency part.

A good EMI/EMC design must be based on the location of the device, the layout of the PCB stack, the important way of moving the device, the choice of the device, etc., if these are not better arrangements beforehand, afterwards It will take half the effort and increase the cost. For example, the position of the clock generator should not be close to the external connector. The high-speed signal should go as far as possible to the inner layer and pay attention to the characteristic impedance matching and the continuity of the reference layer to reduce the reflection. The slope of the signal pushed by the device (slew rate As small as possible to reduce high frequency components, choose decoupling/bypass capacitors to pay attention to whether the frequency response meets the requirements to reduce the power layer noise. In addition, pay attention to the return path of high frequency signal current to make the loop area as small as possible (also It is the loop impedance loopimpedance as small as possible to reduce the radiation. It is also possible to divide the formation to control the range of high frequency noise. Finally, properly select the chassis ground of the PCB and the enclosure.

31. How to choose EDA tools?

In the current PCB design software, thermal analysis is not a strong point, so it is not recommended. Other functions 1.3.4 can choose PADS or Cadence performance price ratio is good. Beginners of PLD design can use the integrated environment provided by PLD chip manufacturers, and can use single point tools when designing more than one million gates.

32. Please recommend an EDA software suitable for high speed signal processing and transmission.

With conventional circuit design, INNOVEDA's PADS is very good, and there are simulation software that works together, and this type of design often occupies 70% of applications. In high-speed circuit design, analog and digital hybrid circuits, Cadence's solution should be a relatively good performance software. Of course, Mentor's performance is still very good, especially its design process management should be the best.

33. Explanation of the meaning of each layer of the PCB

Topoverlay ---- top device name, also known as top silkscreen or top component legend, such as R1 C5, IC10.bottomoverlay----multi-layer-----If you design a 4-layer board, you put a free pad Or via, define it as multilay, then its pad will automatically appear on the 4 layers. If you only define it as the top layer, then its pad will only appear on the top layer.

34. 2G above high-frequency PCB design, routing, typesetting, should pay attention to what aspects?

High-frequency PCBs above 2G are RF circuit designs and are not covered by high-speed digital circuit design. The layout and routing of the RF circuit should be considered together with the schematic, as the layout will cause a distribution effect. Moreover, the RF circuit design of some passive components is realized by parameterized definition, special shape copper foil, so EDA tools are required to provide parametric devices and to edit special shape copper foil. Mentor's boardstation has dedicated RF design modules to meet these requirements. Moreover, general RF design requires specialized RF circuit analysis tools. The industry's best known is agilent's eesoft, which has a good interface with Mentor's tools.

35. 2G above high-frequency PCB design, what rules should be followed in the design of microstrip?

RF microstrip line design requires 3D field analysis tools to extract transmission line parameters. All rules should be specified in this field extraction tool.

36. For a full digital signal PCB, there is an 80MHz clock source on the board. In addition to the use of wire mesh (grounding), what circuit should be used to protect it in order to ensure sufficient driving capability?

To ensure that the drive capability of the clock should not be achieved through protection, a clock driver chip is generally used. The general concern about clock drive capability is due to multiple clock loads. Using a clock driver chip, a clock signal is turned into several, using a point-to-point connection. Select the driver chip, in addition to ensuring a basic match with the load, the signal edge meets the requirements (generally the clock is along the valid signal). When calculating the system timing, it is necessary to count the clock delay in the driver chip.

37. If a separate clock signal board is used, what kind of interface is generally used to ensure that the transmission of the clock signal is less affected?

The shorter the clock signal, the smaller the transmission line effect. Using a separate clock signal board increases the signal routing length. Moreover, the grounding power supply of the board is also a problem. For long distance transmission, a differential signal is recommended. The LVDS signal can meet the drive capability requirements, but your clock is not too fast and not necessary.

38. 27M, SDRAM clock lines (80M-90M), the second and third harmonics of these clock lines are just in the VHF band, and the interference is very high after the high frequency intrusion from the receiving end. In addition to shortening the line length, what better way?

If the third harmonic is large, the second harmonic is small, probably because the signal duty cycle is 50%, because in this case, the signal has no even harmonics. At this time, you need to modify the signal duty cycle. In addition, for a clock signal that is unidirectional, source-side series matching is generally used. This suppresses secondary reflections but does not affect the clock edge rate. The source matching value can be obtained by the formula below.

39. What is the topology of the trace?

Topology, some is also called routing order. The routing order for networks with multi-port connections.

40. How to adjust the topology of the trace to improve signal integrity?

This kind of network signal direction is more complicated, because the unidirectional, bidirectional signal, different level signal, the topology effect is different, it is difficult to say which topology is beneficial to the signal quality. Moreover, when doing pre-simulation, what kind of topology is used is very demanding for engineers, and it is required to understand the circuit principle, signal type, and even wiring difficulty.


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