1. Series termination matching
The theoretical starting point of series termination matching is that a resistor R is connected in series between the source end of the signal and the transmission line under the condition that the signal source impedance is lower than the characteristic impedance of the transmission line, so that the output impedance of the source end matches the characteristic impedance of the transmission line, and the suppression is performed. The signal reflected back from the load end is reflected again.
The signal transmission after serial terminal matching has the following characteristics:
A. Due to the action of the series matching resistor, the driving signal propagates to the load end with 50% of its amplitude;
B. The reflection coefficient of the signal at the load end is close to +1, so the amplitude of the reflected signal is close to 50% of the amplitude of the original signal.
C. The reflected signal is superimposed with the signal propagated at the source end, so that the signal received by the load end is approximately the same as the amplitude of the original signal;
D. The reflected signal of the load end propagates to the source end, and is absorbed by the matching resistor after reaching the source end;
E. After the reflected signal reaches the source, the source drive current drops to 0 until the next signal transmission.
For parallel matching, series matching does not require a large current drive capability of the signal driver.
The principle of selecting the series termination matching resistance value is simple, that is, the sum of the matching resistance value and the output impedance of the driver is required to be equal to the characteristic impedance of the transmission line. The ideal signal driver's output impedance is zero, the actual driver always has a relatively small output impedance, and the output impedance may be different when the signal level changes. For example, a CMOS driver with a supply voltage of +4.5V has a typical output impedance of 37Ω at low level and a typical output impedance of 45Ω at high level ; the TTL driver and CMOS driver have the same output impedance as the signal The level changes as the level changes. Therefore, for TTL or CMOS circuits, it is impossible to have a very correct matching resistor, which can only be considered.
The signal network of the chain topology is not suitable for series termination matching, and all loads must be connected to the end of the transmission line. Otherwise, the waveform received by the load in the middle of the transmission line will be the same as the voltage waveform at point C in Figure 3.2.5. It can be seen that there is a time when the load side signal amplitude is half of the original signal amplitude. Obviously, the signal is in an indeterminate logic state at this time, and the noise margin of the signal is very low.
Series matching is the most common method of terminal matching. It has the advantage of low power consumption, no additional DC load on the driver, no additional impedance between the signal and ground, and only one resistor component.
2. Parallel terminal matching
The theoretical starting point of parallel terminal matching is to eliminate the characteristic impedance of the transmission line by increasing the shunt resistance when the impedance of the signal source is small, so as to eliminate the reflection at the load end. The implementation form is divided into two forms: single resistance and double resistance.
The signal transmission after parallel terminal matching has the following characteristics:
A. The drive signal propagates approximately along the transmission line at full amplitude;
B. All reflections are absorbed by the matching resistors;
C. The amplitude of the signal received by the load is approximately the same as the amplitude of the signal sent by the source.
In the actual circuit system, the input impedance of the chip is very high, so for the single-resistance form, the parallel resistance value of the load terminal must be close to or equal to the characteristic impedance of the transmission line. Assuming that the characteristic impedance of the transmission line is 50 Ω, the R value is 50 Ω. If the signal's high level is 5V, the quiescent current of the signal will reach 100mA. Due to the small driving capability of typical TTL or CMOS circuits, this parallel matching of single resistors is rarely found in these circuits.
Parallel matching in the form of a double resistor, also known as the Thevenin termination, requires less current drive capability than a single resistor form. This is because the parallel values of the two resistors match the characteristic impedance of the transmission line, and each resistor is larger than the characteristic impedance of the transmission line. Considering the driving capability of the chip, the choice of two resistor values must follow three principles:
(1). The parallel value of the two resistors is equal to the characteristic impedance of the transmission line;
(2). The resistance value connected to the power supply should not be too small to avoid excessive driving current when the signal is low.
(3). The value of the resistor connected to ground should not be too small to prevent the drive current from being too high when the signal is high.
The advantage of parallel termination matching is simple and easy; the obvious disadvantage is the DC power consumption: the DC power consumption of the single-resistance mode is closely related to the duty cycle of the signal. The dual-resistance mode has DC power regardless of whether the signal is high or low. Therefore, it is not suitable for systems with high power consumption, such as battery-powered systems. In addition, the single-resistance method is not applied in general TTL and CMOS systems due to the driving capability problem, and the two-resistor method requires two components, which imposes requirements on the board area of the PCB, and thus is not suitable for high-density printed circuit boards. .
Of course, there are: AC terminal matching; diode-based voltage clamping and other matching methods.
3. Consequences of poor impedance matching
Since the "characteristic impedance" (Z0) of high-frequency signals is very long, it is generally referred to as "impedance". The reader must be careful that the impedance (Z) that appears in the wires (not the transmission line) of the low-frequency AC (60 Hz) is not exactly the same. Digital system When the Z0 of the entire transmission line can be properly managed, and the control is within a certain range (±10% or ±5%), this good quality transmission line will reduce the noise, and the malfunction can also be avoided.
However, when any of the four variables (w, t, h, r) of Z0 in the above microstrip line is abnormal, such as a gap in the signal line, the original Z0 will suddenly rise (see Z0 in the above formula). When W is inversely proportional to the fact that it cannot continue to maintain its desired stability, the energy of its signal will inevitably partially advance, while the part will lack the rebound reflection. This will not avoid noise and malfunction. For example, the hose for watering is suddenly stepped on, causing an abnormality at both ends of the hose, which just explains the problem of poor impedance matching of the above characteristics.
Poor impedance matching causes noise
The rebound of the above part of the signal energy will cause the original good quality square wave signal to immediately appear abnormal deformation (that is, the high-level upward Overshoot occurs, the low-level down Undershoot, and the subsequent Ringing). When such high-frequency noise is severe, it may cause malfunction, and the faster the pulse speed, the more the noise is more error-prone.