The current typical design environment is mostly oriented to the later stages of design, with board drawing as the main consideration. Design tool providers are now working on these new design challenges. But design engineers need a new way to solve the increasingly high-speed design problems in design, which allows design engineers to solve problems early in the design process.
Closer tool integration
To find and solve these high-speed signal problems without relying on expensive and time-consuming board testing steps, the key is to perform a large amount of signal analysis before board design. When design engineers discover these problems, they can ensure a one-time success in circuit design by changing the layout of the wiring and circuit layers, defining the routing topology of the clock lines, and selecting components of a particular speed.
However, previous signal integrity analysis tools have significant limitations, either not easy to use or have the ability to analyze the entire design. Therefore, design engineers can only rely on experience to determine the critical circuit network that needs to be focused, or rely on a comprehensive analysis tool for signal integrity.
Recently, design tools have begun to make new breakthroughs and develop effective analysis tools for high-speed design problems. Taking the signal integrity analysis tool provided by Innoveda as an example, the company's HyperLynx tool set is easy to use and provides powerful signal integrity analysis before and after board drawing. One of its outstanding features is the user-friendly interface, which allows design engineers to quickly analyze the "possible conditions" they envision and experiment with issues such as terminal topologies to quickly find the best performance and reliability. solution. For those engineers dealing with high-complexity boards and systems, Innoveda's XTK Signal Integrity Verification Tool Set and ePlanner Signal Integrity Planning Environment provide advanced algorithms for ultra-high-speed signal integrity analysis and some proven verification Features include topological analysis, high-speed scanning and lossy lines, Monte Carlo methods, and advanced algorithms for signal integrity analysis.
In the past, design engineers had to choose between Hyperlynx and XTK. Recently, Innoveda implemented a connection between these two key signal integrity analysis tools, which integrates the two and allows both tools to be used in a single design, effectively reducing design cycles. Typically, HyperLynx was originally used as a tool for high-speed PCB signal analysis, while XTK and ePlanner were used for more complex topology analysis and constraint generation.
Enhanced wiring capability
After determining the routing rules, the design engineer began to move into the physical implementation of the design. The usual PCB drawing tools provide comprehensive component selection capabilities, the ability to set board layers, assign constraint rules, and manage the placement of all components on the board. Good tools must be easy to use, automatically manage all design constraints and produce the final board design.
But this is not enough in a high-speed design environment, PCB mapping tools must provide a more comprehensive solution. At present, some designs are usually very complicated, and the development time is short. The design engineers can no longer use the manual drawing method in the past, otherwise it is time consuming and error-prone. To maximize productivity and solve a large number of signal analysis problems, design engineers need a tool that allows them to do both batch and interactive routing.
Innoveda's latest release of PowerPCB 5.0 meets this design requirement. This shape and rule based board design system includes the BlazeRouter HSD (High Speed Design), a high speed design option that allows automatic routing based on high speed constraints including minimum/maximum length, match length and differential paIR. Such constraints can be placed anywhere in the rules system, and BlazeRouter HSD can automatically implement the design according to these rules. This allows design engineers to set and protect critical circuit topologies to ensure critical signals are connected in the correct order.
The tool also adds interactive routing editors to design engineers who are happy to manually route and provides a number of special support for networks created by constraints. This new Fast Interactive Wiring Editor (FIRE) features a variety of Design Rule Check (DRC) modes and new wiring editing features. Design engineers can automatically add "Z" jacks to find differential pairs, monitor trace lengths, or design according to specific constraint rules. This allows design engineers to more easily implement dense wiring designs and achieve greater wiring density on a minimum of layers.
In addition, the tool provides a graphical feedback function that indicates to the design engineer the impact of a cabling selection on other boards on the board. In the past, it was difficult for design engineers to know how changes to critical networks affected other parts of the design. BlazeRouter HSD graphically expresses these previously difficult-to-understand effects, with different colors and brightness to indicate different effects. This can help design engineers understand the possible impact of each cabling option.
Establish a complete design approach
These tools represent the most important developments in the current high-speed issues that are common in today's board designs. However, design tools must add more features to accommodate the rapidly growing clock speed and complexity of board design, especially with a comprehensive design approach that replaces today's multipoint design tools.
What is the design process for the new method? To address high-speed issues in critical paths, new features must be added during the initial design definition phase of the process. To achieve this, the new method must have strong simulation and analysis capabilities. At the same time, you must be able to understand the key data of the board design, especially regarding the availability and cost of components. Ideally, design engineers can collaborate across the company through design platforms. Design engineers can communicate design ideas between design engineers through the network, as well as communicate with other departments such as procurement and production.
At the same time, the design of high-speed boards relies heavily on a constraint generation method. Currently, design engineers enter electronic design data and design constraints into board drawing software to implement circuit design, but the increasing complexity of signal integrity issues and board design complicates the problem. To solve the signal integrity problems on these high speed and complex boards, they must simulate and synthesize the design before drawing the board. This puts new demands on the design environment. From electrical characteristics to manufacturing processes, design engineers must develop constraints. On an ideal design platform, design engineers can not only set electrical characteristics rules for parameters such as trace length, electromagnetic interference, or crosstalk, but also set component placement rules for component spacing, height limits, and rotation angles.
In order to quickly generate such constraints, the design environment must have strong topological analysis and "possible case" analysis capabilities. It is best to allow design engineers to design and simulate network topologies in circuit diagrams, allowing signal integrity analysis engines to change topology parameters in multiple simulations, and then to study various termination schemes and delay constraints, circuits Layer options and trace spacing work together to minimize the effects of signal integrity. This functionality should also be closely tied to the placement of the components and tied to the planning function so that the design engineer can define the initial component placement and understand the performance of the routing strategy. All in all, the new design environment must provide strong constraint management capabilities so that design engineers can organize and manage a wide range of information.
Not only that, but this new approach to high-speed design must also provide verification capabilities later in the development process. In the past, circuit design engineers only performed post-wiring verification when there was a critical network on the board, and a complete comprehensive verification of the entire board design was considered complicated and time consuming. But this view is changing, because today's high-speed board design, the complex interaction between thousands of networks is difficult to predict. The only way to ensure the reliability of the design is to thoroughly simulate the entire wiring design.
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