Properplacement of the proper capacitance near the power pins of the IC can make theIC output voltage jump faster. However, the problem is not here. Due to thelimited frequency response of the capacitor, this makes it impossible for thecapacitor to generate the harmonic power needed to drive the IC output cleanlyacross the entire frequency band. In addition, the transient voltage developedacross the power rail creates a voltage drop across the decoupling inductor andthese transient voltages are the main source of common mode EMI. How should wesolve these problems?
ForICs on our boards, the power planes around the IC can be thought of asexcellent high frequency capacitors that collect the amount of energy leakedfrom discrete capacitors that provide high frequency energy for clean outputs.In addition, the excellent power layer inductance is small, so the transientsignal synthesized by the inductor is small, thus reducing the common mode EMI.
Ofcourse, the connection of the power plane to the IC power pin must be as shortas possible, since the rising edge of the digital signal is faster and faster,preferably directly connected to the pad where the IC power pins are located,as discussed further.
Tocontrol common-mode EMI, the power plane must contribute to decoupling and havea sufficiently low inductance. The power plane must be a well-designed powerplane pair. One might ask, how good is it to be good? The answer to thequestion depends on the delamination of the power supply, the materials of thelayers, and the frequency of operation (ie, the IC rise time). Normally, thepower supply is separated by 6mils and the interlayer is FR4, the equivalentcapacitance per square inch of the power plane is about 75pF. Obviously, thesmaller the interlayer spacing, the larger the capacitance.
Thereare not many devices with rise times of 100 to 300 ps, but at the current rate ofIC development, devices with rise times in the 100 to 300 ps range will occupya high percentage. For circuits with 100 to 300ps rise time, 3mil layer spacingwill no longer apply for most applications. At that time, it is necessary touse a layering technique with a layer spacing of less than 1 mil and replacethe FR4 dielectric with a material of high dielectric constant. Today, ceramicand pottery plastics meet the design requirements of 100 to 300 ps rise timecircuits.
Althoughnew materials and new methods may be introduced in the future, 3 to 6 milspacing and FR4 dielectrics are common enough today for high 1-to-3 ns risetime circuits, enough to handle high-end harmonics and to make transientsignals low enough, Common mode EMI can be lowered very low. The examples givenin this paper for the design of a hierarchical stack of PCBs will assume alayer spacing of 3 to 6 mils.
Fromthe signal routing point of view, a good strategy should be layered stratifiedsignal routing on one or several layers, these layers next to the power orground plane. For power supply, a good strategy of stratification should beadjacent to the power plane and ground plane, and the distance between thepower plane and the ground plane is as small as possible. This is what we callthe "layering" strategy.
Whatkind of stacking strategy helps to shield and suppress EMI? The followinglayering scheme assumes that the supply current flows on a single layer withsingle or multiple voltages distributed in different parts of the same layer.Multi-power layer situation to be discussed later.
Thereare several potential issues with the 4-layer board design. First of all, thetraditional four-layer board with a thickness of 62 mil, even if the signallayer is in the outer layer, the power source and the ground layer are in theinner layer, the distance between the power layer and the ground layer is stilltoo large.
Ifthe cost requirements are first, consider the following two alternatives totraditional 4-layer boards. Both of these solutions improve the performance ofEMI suppression, but only for applications where the on-board component densityis low enough and there is enough area around the component where the requiredpower supply copper layer is placed.
Thefirst is the preferred solution, the outer layer of the PCB are strata, the middletwo layers are the signal / power layer. The power supply on the signal layeris routed with a wide line, which lowers the path impedance of the supplycurrent and lowers the impedance of the signal microstrip path. From the EMIcontrol point of view, this is the best 4-layer PCB structure available. Thesecond option to go the outer power source and the ground, take the middle twofloors signal. Compared with the traditional 4-layer board, the improvement issmaller, and the interlayer impedance is not as good as the traditional 4-layerboard.
Ifyou want to control the trace impedance, the above stack scheme must be verycareful to route the layout in the power and ground below the copper islands.In addition, the power supply or strata should be interconnected as much aspossible between the copper islands to ensure DC and low frequencyconnectivity.
Ifthe 4-layer board component density is relatively large, it is best to use6-layer board. However, some laminate schemes in the 6-layer board design arenot good enough to shield the electromagnetic field and have little effect onreducing the transient signal of the power bus. Two examples are discussedbelow.
Thefirst case places the power supply and ground on the 2nd and 5th floors,respectively. Due to the high copper resistance of the power supply, it is veryunfavorable to control the common mode EMI radiation. However, this approach isquite correct from the viewpoint of signal impedance control.
Thesecond example places power and ground on the 3rd and 4th floors, respectively.This design solves the problem of copper-clad power. Due to poorelectromagnetic shielding performance of the 1st and 6th floors, differentialmode EMI increases. This design solves the problem of differential mode EMI ifthe number of signal lines on both outer layers is minimum and the trace lengthis short (less than 1/20 of the wavelength of the highest harmonic of thesignal). Suppressing the differential mode EMI is particularly good whencopper-free copper-free areas and copper-free areas are patched on the outerlayer with no components and no trace areas (every 1/20 wavelength interval).As mentioned earlier, it is necessary to connect the copper shop with theinternal ground floor.
Generalhigh-performance 6-layer board design generally layer 1 and layer 6 as astratum, the first 3 and 4 go power and ground. EMI suppression is excellentdue to the double-layer, double-layer signal line layer centered between thepower plane and the ground plane. The disadvantage of this design is that thewiring layer has only two layers. As mentioned earlier, if the outer traces areshort and copper is removed in a trace-free area, the same stack can beachieved with a traditional 6-layer board.
Another6-layer board layout for the signal, ground, signal, power, ground, signal,which can achieve the advanced signal integrity design environment. The signallayer is adjacent to the ground plane, and the power plane and ground plane arepaired. Obviously, the downside is that the layers of the stack are unbalanced.
Thisusually causes problems for manufacturing. The solution to this problem is tofill all the blank areas of the third layer with copper. If the copper densityof the third layer is close to that of the power layer or the ground layerafter the copper is filled, the board may not be strictly counted as a circuitboard with a balanced structure. Copper area must be connected to power orground. The distance between the connecting vias is still 1/20 of the wavelength,not necessarily everywhere, but ideally should be connected.
Dueto the very thin insulating isolation between the multilayer boards, theimpedance between the 10 or 12-layer board layers is very low and excellentsignal integrity is perfectly expected as long as there is no problem withdelamination and stacking. To 62mil thickness processing 12-layer boardmanufacturing, more difficult to process 12-layer board manufacturers are notmany.
Sincethe signal layer and the circuit layer is always separated by insulationbetween the 10-layer board design to distribute the middle six layers to gosignal line is not the best solution. In addition, it is important that thesignal layer and the circuit layer are adjacent to each other, that is, theboard layout is signal, ground, signal, signal, power, ground, signal, signal,ground, and signal.
Thisdesign provides a good path for the signal current and its return current. Theproper routing strategy is that the first layer is routed in the X direction,the third layer is routed in the Y direction, the fourth layer is routed in theX direction, and so on. Intuitively looking at the alignment, Layers 1 and 3are a pair of tiered layers, Layers 4 and 7 are a pair of tiered layers, and Layers8 and 10 are the last pair of tiered layers. When you need to change thedirection of alignment, the signal line on layer 1 should be "vias"to layer 3 and then change direction. In fact, this may not always be the case,but as a design concept, you should still try to follow it.
Similarly,when the alignment of the signal changes, it should be through the vias fromthe 8th floor and the 10th floor or from the 4th floor to the 7th floor. Thisrouting ensures that the coupling between the signal's forward path and theloop is the tightest. For example, if the signal is routed on layer 1 and thecircuit is routed on layer 2 and only on layer 2, the signal on layer 1 isrouted to layer 3 via "vias," The loop is still level 2, maintaininglow inductance, large capacitance characteristics and good electromagneticshielding.
Ifthe actual alignment is not the case, how to do? For example, the signal linethrough the first layer through the hole to the 10th layer, then the loopsignal from the 9th layer to find the ground plane, the loop current to findthe nearest ground vias Resistors or capacitors and other components of theground pin). If you happen to exist near such vias, you are really lucky. Ifthere is no such near-hole available, the inductor will become larger, thecapacitor should be reduced, EMI will increase.
Whenthe signal line must leave the current pair of wiring layers to the otherwiring layers via the via holes, the ground vias should be placed near the viaholes nearby so that the loop signal can be smoothly returned to the properground plane. For tiered layer 4 and layer 7 combinations, the signal loop willreturn from the power plane or ground plane (ie, Layer 5 or 6) because thecapacitive coupling between the power plane and the ground plane is good andthe signal is easy to transmit.
Iftwo power planes of the same voltage source need to output a large current, thecircuit board should be distributed into two power planes and a ground plane.In this case, an insulating layer is placed between each pair of power andground planes. This gives us two equally-divided pairs of impedances equal tothe current we expect. If the stack of power planes causes the impedances to beunequal, the shunt is not uniform, the transient voltage will be much larger,and the EMI will increase dramatically.
Ifmultiple numerically different supply voltages exist on the board, multiplepower planes are required accordingly, keeping in mind that separate matedpower planes and ground planes are created for different power sources. In bothcases, make sure that the paired power and ground planes are at the circuitboard's location, bearing in mind the manufacturer's requirements for abalanced structure.
To sum up
Sincemost engineers design the circuit board to be 62mil thick, with no traditionalPCBs with blind holes or buried holes, the discussion of board delamination andstacking in this article is limited to this. Thickness difference between thecircuit board is too thick, the layered scheme recommended in this article maynot be ideal. In addition, with blind hole or buried circuit board processingprocess is different, the method of stratification of this article does notapply.
Circuitboard design thickness, through-hole process and the number of layers of thecircuit board is not the key to solve the problem, excellent stratification isto ensure that the power bus bypass and decoupling, the power layer or groundlayer on the minimum transient voltage And the signal and power of theelectromagnetic shielding the key. Ideally, there should be an insulatingbarrier between the signal routing layer and its return path ground plane, andthe paired layer spacing (or more than one pair) should be as small aspossible. Based on these basic concepts and principles, we can design a circuitboard that always meets the design requirements. Now that the rise time of theIC is already very short and will be shorter, the techniques discussed in thisarticle are necessary to solve EMI shielding issues.