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How to solve the EMI problem of multi-layer PCB design

Posted:04:37 PM December 13, 2017 writer: G

How to solve the EMI problem of multi-layer PCB design

Power bus 

Proper placement of the proper capacitance near the power pins of the IC can make the output voltage jump faster. However, the problem is not here. Due to the limited frequency response of the capacitor, this makes it impossible for the capacitor to generate the harmonic power needed to drive the IC output cleanly across the entire frequency band. In addition, the transient voltage developed across the power rail creates a voltage drop across the decoupling inductor and these transient voltages are the main source of common-mode EMI. How should we solve these problems? 

ForICs on our boards, the power planes around the IC can be thought of as excellent high-frequency capacitors that collect the amount of energy leaked from discrete capacitors that provide high-frequency energy for clean outputs. In addition, the excellent power layer inductance is small, so the transient signal synthesized by the inductor is small, thus reducing the common mode EMI. 

Of course, the connection of the power plane to the IC power pin must be as short as possible, since the rising edge of the digital signal is faster and faster, preferably directly connected to the pad where the IC power pins are located, as discussed further. 

To control common-mode EMI, the power plane must contribute to decoupling and have sufficiently low inductance. The power plane must be a well-designed power plane pair. One might ask, how good is it to be good? The answer to the question depends on the delamination of the power supply, the materials of the layers, and the frequency of operation (ie, the IC rise time). Normally, the power supply is separated by 6mils and the interlayer is FR4, the equivalent capacitance per square inch of the power plane is about 75pF. Obviously, the smaller the interlayer spacing, the larger the capacitance. 

There are not many devices with rising times of 100 to 300 ps, but at the current rate of development, devices with rising times in the 100 to 300 ps range will occupy a high percentage. For circuits with 100 to 300ps rise time, 3mil layer spacing will no longer apply for most applications. At that time, it is necessary to use a layering technique with a layer spacing of less than 1 mil and replace the FR4 dielectric with a material of high dielectric constant. Today, ceramic and pottery plastics meet the design requirements of 100 to 300 ps rise time circuits. 

Although new materials and new methods may be introduced in the future, 3 to 6 mil spacing and FR4 dielectrics are common enough today for high 1-to-3 ns rise time circuits, enough to handle high-end harmonics and to make transient signals low enough, Common mode EMI can be lowered very low. The examples given in this paper for the design of a hierarchical stack of PCBs will assume a layer spacing of 3 to 6 mils. 

Electromagnetic shielding 

From the signal routing point of view, a good strategy should be layered stratifiedsignal routing on one or several layers, these layers next to the power or ground plane. For power supply, a good strategy of stratification should be adjacent to the power plane and ground plane, and the distance between the power plane and the ground plane is as small as possible. This is what we call the "layering" strategy. 

PCB stack 

What kind of stacking strategy helps to shield and suppress EMI? The following layering scheme assumes that the supply current flows on a single layer with single or multiple voltages distributed in different parts of the same layer. Multi-power layer situation to be discussed later. 

4-layer board

There are several potential issues with the 4-layer board design. First of all, the traditional four-layer board with a thickness of 62 mils, even if the signal layer is in the outer layer, the power source and the ground layer are in the inner layer, the distance between the power layer and the ground layer is still too large. 

If the cost requirements are first, consider the following two alternatives to traditional 4-layer boards. Both of these solutions improve the performance of EMI suppression, but only for applications where the onboard component density is low enough and there is enough area around the component where the required power supply copper layer is placed. 

The first is the preferred solution, the outer layer of the PCB is strata, the middle two layers are the signal/power layer. The power supply on the signal layers routed with a wide line, which lowers the path impedance of the supply current and lowers the impedance of the signal microstrip path. From the EMI control point of view, this is the best 4-layer PCB structure available. The second option to go to the outer power source and the ground, take the middle two floors signal. Compared with the traditional 4-layer board, the improvement is smaller, and the interlayer impedance is not as good as the traditional 4-layer board. 

If you want to control the trace impedance, the above stack scheme must be very careful to route the layout in the power and ground below the copper islands. In addition, the power supply or strata should be interconnected as much as possible between the copper islands to ensure DC and low-frequency connectivity. 



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6-layer board 

If the 4-layer board component density is relatively large, it is best to use6-layer board. However, some laminate schemes in the 6-layer board design are not good enough to shield the electromagnetic field and have little effect on reducing the transient signal of the power bus. Two examples are discussed below. 

The first case places the power supply and ground on the 2nd and 5th floors, respectively. Due to the high copper resistance of the power supply, it is very unfavorable to control the common mode EMI radiation. However, this approach is quite correct from the viewpoint of signal impedance control. 

The second example places power and ground on the 3rd and 4th floors, respectively. This design solves the problem of copper-clad power. Due to poor electromagnetic shielding performance of the 1st and 6th floors, differential mode EMI increases. This design solves the problem of differential mode EMI if the number of signal lines on both outer layers is minimum and the trace length is short (less than 1/20 of the wavelength of the highest harmonics of the signal). Suppressing the differential mode EMI is particularly good when copper-free copper-free areas and copper-free areas are patched on the outer layer with no components and no trace areas (every 1/20 wavelength interval). As mentioned earlier, it is necessary to connect the copper shop with the internal ground floor. 

General high-performance 6-layer board design generally layer 1 and layer 6 as stratum, the first 3 and 4 go power and ground. EMI suppression is excellent due to the double-layer, double-layer signal line layer centered between the power plane and the ground plane. The disadvantage of this design is that the wiring layer has only two layers. As mentioned earlier, if the outer traces are short and copper is removed in a trace-free area, the same stack can be achieved with a traditional 6-layer board. 

Another6-layer board layout for the signal, ground, signal, power, ground, signal, which can achieve the advanced signal integrity design environment. The signal layer is adjacent to the ground plane, and the power plane and ground plane repaired. Obviously, the downside is that the layers of the stack are unbalanced. 

This usually causes problems for manufacturing. The solution to this problem is to fill all the blank areas of the third layer with copper. If the copper density of the third layer is close to that of the power layer or the ground layer after the copper is filled, the board may not be strictly counted as a circuit board with a balanced structure. The copper area must be connected to power or ground. The distance between the connecting vias is still 1/20 of the wavelength, not necessarily everywhere, but ideally should be connected. 

10-layer board 

Due to the very thin insulating isolation between the multilayer boards, the impedance between the 10 or 12-layer board layers is very low, and excellent signal integrity is perfectly expected as long as there is no problem with delamination and stacking. To 62mil thickness processing 12-layer board manufacturing, more difficult to process 12-layer board manufacturers are not many. 

Since the signal layer and the circuit layer are always separated by insulation between the 10-layer board design to distribute the middle six layers to the signal line is not the best solution. In addition, it is important that the signal layer and the circuit layer are adjacent to each other, that is, the board layout is signal, ground, signal, signal, power, ground, signal, signal, ground, and signal. 

This design provides a good path for the signal current and its return current. The proper routing strategy is that the first layer is routed in the X direction, the third layer is routed in the Y direction, the fourth layer is routed in the direction, and so on. Intuitively looking at the alignment, Layers 1 and 3are a pair of tiered layers, Layers 4 and 7 are a pair of tiered layers, and Layers8 and 10 are the last pair of tiered layers. When you need to change the direction of alignment, the signal line on layer 1 should be "vias"to layer 3 and then change direction. In fact, this may not always be the case, but as a design concept, you should still try to follow it. 

Similarly, when the alignment of the signal changes, it should be through the vias from the 8th floor and the 10th floor or from the 4th floor to the 7th floor. This routing ensures that the coupling between the signal's forward path and the loop is the tightest. For example, if the signal is routed on layer 1 and the circuit is routed on layer 2 and only on layer 2, the signal on layer 1 is routed to layer 3 via "vias," The loop is still level 2, maintaining low inductance, large capacitance characteristics and good electromagnetic shielding. 

If the actual alignment is not the case, how to do it? For example, the signal line through the first layer through the hole to the 10th layer, then the loop signal from the 9th layer to find the ground plane, the loop current to find the nearest ground vias Resistors or capacitors, and other components of the ground pin). If you happen to exist near such vias, you are really lucky. If there is no such near-hole available, the inductor will become larger, the capacitor should be reduced, EMI will increase. 

When the signal line must leave the current pair of wiring layers to the other wiring layers via the via holes, the ground vias should be placed near the via holes nearby so that the loop signal can be smoothly returned to the proper ground plane. For tiered layer 4 and layer 7 combinations, the signal loop will return from the power plane or ground plane (ie, Layer 5 or 6) because the capacitive coupling between the power plane and the ground plane is good and the signal is easy to transmit. 

Multi-power layerdesign 

If two power planes of the same voltage source need to output a large current, the circuit board should be distributed into two power planes and a ground plane. In this case, an insulating layer is placed between each pair of power and ground planes. This gives us two equally divided pairs of impedances equal to the current we expect. If the stack of power planes causes the impedances to be unequal, the shunt is not uniform, the transient voltage will be much larger, and the EMI will increase dramatically. 

If multiple numerically different supply voltages exist on the board, multiple power planes are required accordingly, keeping in mind that separate mated power planes and ground planes are created for different power sources. In both cases, make sure that the paired power and ground planes are at the circuit board's location, bearing in mind the manufacturer's requirements for a balanced structure. 


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Since most engineers design the circuit board to be 62mil thick, with no traditional pubs with blind holes or buried holes, the discussion of board delamination and stacking in this article is limited to this. The thickness difference between the circuit board is too thick, the layered scheme recommended in this article may not be ideal. In addition, with blind hole or buried circuit board processing process is different, the method of stratification of this article does not apply. 

Circuit board design thickness, through-hole process, and the number of layers of the circuit board is not the key to solve the problem, excellent stratification is to ensure that the power bus bypass and decoupling, the power layer or ground layer on the minimum transient voltage And the signal and power of the electromagnetic shielding the key. Ideally, there should be an insulating barrier between the signal routing layer and its return path ground plane, and the paired layer spacing (or more than one pair) should be as small as possible. Based on these basic concepts and principles, we can design a circuit board that always meets the design requirements. Now that the rise time of the IC is already very short and will be shorter, the techniques discussed in this article are necessary to solve EMI shielding issues.

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