The cause and performance of signal integrity
Signal integrity stems from the interconnection of circuits such as wires, substrates, and wells. Since a length of wire is not just an electronic conductor, it is resistive in the low frequency band, capacitive in the middle frequency band, inductive in the high frequency band, and becomes a radiating antenna when it is very high frequency. It is this antenna effect that leads to signal crosstalk and electromagnetic interference (EMI). Since the interaction of carriers in the conductor with atoms and grains produces electrical resistance, as the characteristic size is compressed to less than 0.5 μm, the skin effect causes the metal surface resistance to decrease more slowly than the section resistance, resulting in signal integrity damage. The capacitive effect due to the structure with too close independent voltage increases as the wiring pitch decreases, which has a greater potential impact on the transmission characteristics of the signal. The inductive effect, determined by lead size and return path, is a major concern for package and board design. When the IC size is less than 0.5 μm, the inductance effect becomes very noticeable. There will be significant mutual inductance between the two parallel traces, and some noise will be coupled into the logic circuit, causing the signal to exhibit a completely different phenomenon from the low frequency design. The ability of digital systems to tolerate signal integrity problems is limited. To a certain degree of signal integrity problems, system performance may be degraded or not at all. Simulation results confirm that the IC switching speed is too high, the layout of the termination components is inadequate, and the interconnection of the circuit is unreasonable, which will cause signal integrity problems. Signal integrity mainly includes reflection, crosstalk, oscillation, ground bounce, and so on.
1. Signal reflection
The reflection of the signal is the echo on the transmission line. A portion of the signal power is transmitted to the load via the transmission line and the other portion is reflected to the source. In high-speed design, the conductor can be equivalent to a transmission line instead of a conductor in a lumped parameter circuit, and its transmission effect can be studied by examining its impedance at different frequencies. If the edge rate is as high as 1V/ns (ie, dV/dt), a wire shorter than 0.5 inch can be used to build a T-type concentrating parameter RLC (or RC, LC) model, and multiple T-type cascades are combined into longer Transmission line. In order to reduce the amount of computation of the simulation, a continuous transmission line model can also be established. If the impedance is matched (source impedance, transmission line impedance, and load impedance are equal), reflection will not occur. Conversely, if the load impedance is mismatched with the transmission line impedance, it will cause the end reflection. Signal geometry, improper termination, transmission through the connector, and discontinuity of the power plane can cause signal reflections.
2. Signal overshoot and undershoot
Signal overshoot refers to the first peak (or valley) of a signal transition exceeding a specified value - the highest voltage for a rising edge and the lowest voltage for a falling edge. Undershoot refers to the next valley (or peak) of a signal transition. Signal overshoot and undershoot are caused by excessive IC switching rate and reflection of signal transmission path. Multiple reflections between the driver and the receiver will form a damped oscillation. If the oscillation amplitude exceeds the input switching threshold of the IC, the clock will be wrong. Or the wrong reception of data, excessive overshoot may also cause overvoltage or even damage to components inside the IC.
3. Signal crosstalk
Cross-talk is an electromagnetic coupling phenomenon between an induced voltage and an induced current between signal lines that are not electrically connected. This coupling causes the signal line to act as an antenna, its capacitive coupling induces a coupling current, inductive coupling induces a coupling voltage, and increases with increasing clock speed (resulting in increased edge rate) and reduced design size. Big. This is because when the alternating signal current on the signal line passes, an alternating magnetic field is generated, and other signal lines in the magnetic field induce a signal voltage. In the low frequency band, the coupling between the wires can be established as a coupling capacitance model, and in the high frequency band, it can be established as an LC centralized parameter wire or transmission line model. PCB board layer parameters, signal line spacing, electrical characteristics of the driver and receiver terminals, and signal line termination methods all have a certain impact on crosstalk.
4. Electromagnetic interference
Electromagnetic interference is similar to signal crosstalk. Signal crosstalk is the coupling between two transmission lines that occur on a PCB. The electromagnetic interference is caused by interference from a radiation source outside the PCB (such as a test probe or other PCB board). EMI modeling can treat wire segments as dipole antennas.
5. Signal oscillation and surround
Signal ringing and rounding are characterized by repeated overshoot and undershoot of the signal, shaking up and down the threshold of the logic level, the oscillation is underdamped, and the surround is overdamped. The oscillation and surrounding of the signal is mainly caused by excessive parasitic inductance and capacitance on the transmission line, causing the terminal impedance to be mismatched with the source. As with reflection, they can be suppressed by proper termination. Generally, the periodic pulse signal contains a wealth of higher harmonics and is prone to signal integrity failures, such as clock signals, and should be guarded against.
6. Signal delay
Signal delay indicates that the data or clock signal did not reach the end of the line for a certain amount of time and amplitude within a specified time. The IC can only receive data at a specified timing, and excessive signal delay can cause timing violations and functional clutter. Signal delay is caused by the transmission line effect that drives the overload and the trace is too long. The equivalent capacitance and inductance on the transmission line will delay the digital switching of the signal, affecting the setup time and hold time of the IC. If the delay is too large, the IC will not be able to correctly judge the data.
7. Ground bounce and substrate coupling
Groundbounce is referred to as a ground bounce, which refers to the phenomenon that a large amount of noise is generated between the power source and the ground plane due to a large current surge in the circuit. If a large number of chips are switched synchronously, a large transient current will flow from the chip to the power plane. The parasitic inductance, capacitance and resistance between the chip package and the power supply will cause power supply noise, resulting in a large potential plane. Voltage fluctuations (possibly up to 2v) are sufficient to cause malfunctions of other components. Due to the division of the ground plane (digital ground, analog ground, shielded ground, etc.), it may cause the digital signal to rebound to the ground plane when it goes to the analog ground area. The same power plane split, the same hazard may occur. An increase in load capacitance, a decrease in resistivity, an increase in parasitic parameters, an increase in switching rate, and an increase in the number of synchronous switchings may result in an increase in ground bounce.
At the same time, underlay coupling may make the design more challenging. In silicon design, since the substrate and well have a finite resistivity, a certain voltage drop occurs when a current flows therethrough. The threshold voltage (on) of the MOSFET depends on the effective voltage of the substrate (or well) under the gate, which means that any substrate current can not only cross the threshold voltage of the MOSFET, but also cross the logic gate or clock circuit. The threshold voltage makes the design very unreliable. As the horizontal and vertical dimensions decrease, the resistance of the substrate and well layers increases and the situation becomes worse.