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PCB design tips 100, teach you to master PCB design easily (25-30)

Posted:03:58 PM June 14, 2018 writer: G

how to do a PCB design easily

The increase in the cost of EMC on the PCB board is usually caused by increasing the number of strata to enhance the shielding effect and increasing the suppression of high-frequency harmonic devices such as ferrite bead, choke and so on. In addition, it is usually necessary to match the shielding structure of other organizations to make the whole system meet the requirements of EMC. Here are only a few ways to reduce the electromagnetic radiation produced by the PCB board.

  • 1> chooses the slower slew rate devices as far as possible to reduce the high-frequency components generated by the signals.
  • 2> pay attention to the placement of high-frequency devices, not too close to the external connector.
  • 3> pays attention to the impedance matching of high-speed signals, the return current path, and the line layer, to reduce the high-frequency reflection and radiation.
  • 4> places adequate and appropriate decoupling capacitors at the power pins of each device to ease the noise on the power layer and formation. Pay special attention to whether the frequency response and temperature characteristics of capacitors meet the requirements of design.
  • 5> the ground adjacent to the external connector can be properly separated from the formation, and the ground of the connector will be connected to chassis ground nearby.
  • 6> can properly use ground guard/shunt traces beside some special high-speed signals. But we should pay attention to the influence of guard/shunt traces on the characteristic impedance of the line.
  • 7> power layer is 20H smaller than the formation, and H is the distance between the power layer and the formation.


26. When a PCB board has multiple number / module blocks, it is usual to separate the numbers from modules. Why?

The reason for the separation of the number / mode is that the digital circuit will be in the power and the real estate noise during the high and low potential switching, and the size of the noise is related to the speed and current size of the signal. If the ground plane is not divided and the noise produced by the digital region circuit is large and the circuit of the analog region is very close, the analog signal will still be disturbed by the ground noise even if the signal signal does not cross. That is to say, the mode of non division can only be used in the analog circuit area far away from the large noise digital circuit area.

27. Another approach is to make sure that the number / module is separated from each other, and the whole PCB board is not divided, and the number / mode is connected to the ground plane when the number / mode signal line does not cross each other. What is the truth?

The requirement for the number of analog signals to not cross the line is because the return current path of a fast digital signal will flow back to the source of the digital signal as far as the line below the line. If the digital signal is crossed, the noise generated by the return of the current will appear in the analog circuit area.

28. How to consider impedance matching when designing the schematic diagram of high-speed PCB?

Impedance matching is one of the key elements in designing high-speed PCB circuits. The impedance values have an absolute relationship with the way line, such as the microstrip or the inner layer (stripline/double stripline), the distance from the reference layer (the power layer or the stratum), the line width, the PCB material and so on, which all affect the characteristic impedance of the line. That is to say, the impedance must be determined after wiring. The general simulation software can not take into account some discontinuous wiring conditions due to the limitation of the line model or the mathematical algorithm used. At this time, only some terminators (end connection), such as series resistance, can be reserved on the schematic, to mitigate the effect of the discontinuous line impedance. The real solution to the problem is to avoid the occurrence of impedance discontinuities as far as possible.

29. Where can we provide a more accurate IBIS model library?

The accuracy of IBIS model directly affects the simulation results. Basically, IBIS can be regarded as the electrical characteristic data of the actual chip I/O buffer equivalent circuit, which can generally be converted from the SPICE model (also can be measured, but limited more), and the data of the SPICE has an absolute relationship with the chip manufacturing, so the same device is provided by different chip manufacturers, and the data of the SPICE are different, The data in the transformed IBIS model will vary accordingly. That is to say, if A vendors are used, only they have the ability to provide accurate model data for their devices, because no one else will be more aware of what their devices are made of. If the IBIS provided by the manufacturer is inaccurate, it is the fundamental solution to continuously improve the manufacturer.

30. When designing high-speed PCB, which rules should the designer consider the rules of EMC and EMI?

General EMI/EMC design requires two aspects of both radiation (radiated) and conduction (conducted). The former belongs to a higher frequency part (>30MHz) and the latter is a lower part of the lower frequency (<30MHz). So it is not necessary to pay attention to high frequency but neglecting the low-frequency part. A good EMI /EMC design must take into account the device at the beginning of the layout. Position, the arrangement of the PCB overlapping layer, the important online approach, the selection of the device, and so on. If there is no better arrangement before, it will take half the effort and increase the cost after the event. For example, the position of the clock generator is not close to the external connector, the high-speed signal takes the inner layer as much as possible and pays attention to the characteristic impedance matching and the reference layer. In order to reduce the reflection, the slope of the signal pushed by the device (slew rate) is as small as possible to reduce the high-frequency component. When selecting the decoupling (decoupling/bypass) capacitance, it is noted whether the frequency response is in accordance with the demand to reduce the power layer noise. In addition, it is noted that the return path of the high-frequency signal current makes the loop area as small as possible (that is, loop resistance). Anti-loop impedance is as small as possible to reduce radiation. It can also control the high-frequency noise by dividing the formation. Finally, select the chassis ground of PCB and shell appropriately.


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