Properly placing a capacitor of appropriate capacity near the power supply pin of the IC can make the output voltage of the IC jump faster. However, the problem is not here. Due to the finite frequency response of the capacitor, this makes it impossible for the capacitor to generate the harmonic power required to cleanly drive the IC output over the full frequency band. In addition, the transient voltage developed on the power bus forms a voltage drop across the inductor of the decoupling path, which is the primary source of common-mode EMI interference. How should we solve these problems?
As far as the ICs on our boards are concerned, the power plane around the IC can be thought of as an excellent high-frequency capacitor that collects the energy that is leaked by discrete capacitors that provide high-frequency energy for clean outputs. In addition, the excellent power supply layer has a small inductance, so that the transient signal synthesized by the inductor is also small, thereby reducing common mode EMI.
Of course, the wiring from the power plane to the IC power supply pin must be as short as possible because the rising edge of the digital signal is getting faster and faster, preferably directly to the pad where the IC power supply pin is located. This is discussed separately.
To control common-mode EMI, the power plane must be decoupled and have a low enough inductance. This power plane must be a well-designed pair of power planes. Someone may ask, to what extent is it good? The answer to the question depends on the layering of the power supply, the material between the layers, and the operating frequency (ie, the function of the rise time of the IC). Typically, the power supply is layered at 6 mils and the interlayer is FR4. The equivalent capacitance per square inch of power plane is approximately 75 pF. Obviously, the smaller the layer spacing, the larger the capacitance.
There are not many devices with a rise time of 100 to 300 ps, but according to the current development speed of ICs, devices with a rise time of 100 to 300 ps will occupy a high proportion. For circuits with 100 to 300 ps rise time, the 3 mil layer spacing will no longer be suitable for most applications. At that time, it was necessary to use a layering technique with a layer spacing of less than 1 mil and to replace the FR4 dielectric material with a material having a high dielectric constant. Ceramics and ceramics now meet the design requirements of 100 to 300 ps rise time circuits.
Although new materials and methods may be used in the future, for common 1 to 3 ns rise time circuits, 3 to 6 mil layer spacing, and FR4 dielectric materials, it is usually sufficient to handle high-end harmonics and make the transient signal low enough, that is, Common mode EMI can be reduced very low. The PCB layered stack design example given here will assume a layer spacing of 3 to 6 mils.
From the perspective of signal routing, a good stratification strategy should be to place all signal traces in one or several layers, which are next to the power or ground plane. For power supplies, a good stratification strategy should be that the power plane is adjacent to the ground plane, and the distance between the power plane and the ground plane is as small as possible. This is what we call a "layered" strategy.
What kind of stacking strategy helps shield and suppress EMI? The following layered stacking scheme assumes that the supply current flows on a single layer, with single or multiple voltages distributed across different parts of the same layer. The case of multiple power planes is discussed later.
There are several potential problems with 4-layer board design. First, the conventional four-layer board with a thickness of 62 mil, even if the signal layer is on the outer layer, the power supply and the ground layer are in the inner layer, the distance between the power supply layer and the ground layer is still too large.
If the cost requirement is first, consider the following two alternatives to traditional 4-layer boards. Both of these solutions improve EMI suppression performance, but only for applications where the on-board component density is low enough and there is sufficient area around the component to place the required copper layer on the power supply.
The first is the preferred solution. The outer layers of the PCB are all ground layers, and the middle two layers are signal/power layers. The power supply on the signal plane is routed with a wide line, which allows the path impedance of the supply current to be low and the impedance of the signal microstrip path to be low. From the perspective of EMI control, this is the best 4-layer PCB structure available; the outer layer of the second solution takes the power and ground, and the middle two layers take the signal. Compared with the traditional 4-layer board, the improvement is smaller, and the interlayer resistance is as poor as the traditional 4-layer board.
If you want to control the trace impedance, the above stacking scheme must be very careful to place the traces under the power and ground copper islands; in addition, the copper or islands on the power supply or ground should be interconnected as much as possible. To ensure DC and low frequency connectivity.
If the density of the components on the 4-layer board is relatively large, it is preferable to use a 6-layer board. However, some laminate solutions in the 6-layer board design do not have a good shielding effect on the electromagnetic field, and have little effect on the reduction of the power bus bus transient signal. In the first case, the power and ground were placed on the 2nd and 5th layers respectively. Due to the high impedance of the copper of the power supply, it is very disadvantageous for controlling the common mode EMI radiation. However, from the point of view of signal impedance control, this method is very correct.