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Handling Signal Integrity of High-Speed ​​Board Designs with Serial RapidIO Switching
Posted:12:21 PM October 30, 2018 writer: G

Serial RapidIO switch

Serial RapidIO interconnects can be used to handle some of the signal integrity challenges discussed above. RapidIO is a mature, open standard for inter-chip, inter-board and inter-chassis interconnects, designed by leaders in embedded computing to meet device pairs in wireless infrastructure, networking, storage, scientific, military, and industrial markets. Reliability, cost effectiveness, performance and scalability requirements.

RapidIO is a point-to-point packet-switched interconnect protocol designed to meet the needs of today's and tomorrow's embedded applications. The RapidIO Physical Layer 1x/4x Link Serial Specification addresses the physical layer media requirements of devices using electronic serial connections. This specification defines a full-duplex serial physical layer interface (link) between devices that use unidirectional differential signals. In addition, it allows four serial links to be combined for applications that require higher link performance. It also defines protocols for link management and transport of packets over a link.

The architecture of the RapidIO system consists of the endpoint components and the switch fabric that connects the endpoints. Imagine the endpoint as the starting point in the mail system, and the switch acts as a post office that intercepts the package and sends the package to its destination. The RapidIO interconnect architecture is divided into layered architectures according to specifications, including the logical layer, the common transport layer, and the physical layer. The physical layer of the RapidIO protocol is handled by the chip serializer-deserializer (SerDes). The characteristics of SerDes have a certain impact on the signal integrity issues that hardware designers face when designing boards. Many other aspects of switch design will also affect signal integrity.

RapidIO switching features simplify board design and achieve high signal integrity

Clock generation

As far as the initiator is concerned, the sRIO switch must have a noise-free clock signal that achieves low jitter. The low jitter signal basically has the characteristics of low phase noise. If the input clock signal is increased to achieve a higher frequency output signal, the chip circuit must be optimized to produce minimal phase noise. Tundra's Tsi57x Serial RapdIO switches produce up to 3.125Ghz of output with 125MHz and 155MHz clocks with integrated low noise amplification PLLs. Many products use separate circuits to achieve these functions, so they cannot achieve low jitter like the Tundra switch chip. The clarity of the output signal is also not as good as when using the Tundra switch chip, making it difficult for the board design to tolerate the other board-level signal integrity issues discussed above.

Programmable transmit pre-emphasis and receiver equalization

In high-speed board design, since the signal is transmitted from the chip to the chip or through the backplane through the board, the attenuation of the signal needs to be considered. In short, the actual signal will decrease in intensity as it reaches the endpoint and a phase shift may occur. In general, high frequency harmonics have a higher proportion of lower frequency harmonic attenuation in all media. Enhancing the overall signal alone is not enough because it expands the noise floor and does not solve the phase shift problem. Serial RapidIO switching and endpoints (like all other high-speed designs like GbE and 10GbE) use technology to avoid this problem and maintain the integrity of the original signal.

To understand the effects of transmit pre-emphasis and receiver equalization, you can review the eye diagram with the goal of achieving "open eyes." If these techniques are not used, the eye diagram will begin to “close”.

Transmission pre-emphasis technology adds high frequencies to the transmitted signal to account for signal attenuation and phase shift between the endpoints. Therefore, unlike simply amplifying all frequencies (which also increases the overall power consumption of the switching chip), the transmission pre-emphasis can effectively enhance the output waveform through the transmission function, increasing the high-frequency amount of the output waveform while simultaneously using virtual components. Perform phase shift to resolve the phase shift caused by the transmission medium. This method is quite effective for maintaining signal integrity and maintaining eye diagrams.

Although transmission pre-emphasis is typically used in many high speed ICs to optimize overall system level signal integrity, the "transmission" transmission pre-emphasis should be used in conjunction with the "receiver" receiver equalization. The receiver equalizes the booster transmission function to compensate for high frequency transmission loss and phase shift caused by the board and backplane. Since these transmission losses occur before the signal reaches the destination IC (in this case, the serial RapidIO exchange), the switch must usually take action before the signal is sent to the next transmission part (another exchange) or endpoint in the system. Compensate for these losses. Receiver equalization is similar to transmission pre-emphasis, improving overall signal-to-noise ratio. Note: The links to the switch chip may have different characteristics.

Similarly, the receiver equalization of each link needs to be different and needs to be programmed for use. All of the Tundra RapidIO Tsi57x switches have this feature, and in terms of signal integrity, this feature will greatly simplify system-level design.

Synchronous and asynchronous switching design

The Serial RapidIO standard supports three different link rates: 1.25G baud, 2.5G baud, and 3.125G baud. Exchange can be divided into two categories: synchronous and asynchronous.

Synchronous switching refers to the exchange in which all ports must operate at the same speed.

Asynchronous switching refers to the exchange of ports that can operate at the frequency required for a particular linked traffic demand.

In most applications, the best solution is asynchronous switching, which not only has the advantage of meeting the traffic demands with lower overall system power consumption, but it is also less affected by crosstalk in terms of signal integrity.

Packaging and interconnection

Signal integrity issues can be heavily influenced by packaging and basic material design. For example, high-performance flip-chip and wire bond packages improve power transfer and reduce backhaul losses. For RapidIO switches, it is important to improve impedance matching to maintain 100 ohm differential impedance and low variation. Flip-chip packaging can help improve this.

Efficient spherical mapping

Silicon suppliers may choose to use a spherical mapping to simplify signal transmission from the chip to the ball grid, but its role is not limited to this. Ideally, an overall system-level implementation is considered when designing a spherical map. For example, when designing a spherical map, it is important to remember to link the peripheral IC to the switch chip. The design should be optimized to minimize the number of layers and the required area to improve the signal integrity of the final design. ICs with fairly dense spherical mapping require many layers on the board to send signals out of the IC, resulting in a costly system-level design. Another problem is crosstalk between signal paths, which has been mentioned above when discussing the differences between synchronous and asynchronous RapidIO exchanges. One problem that is closely tied to crosstalk between signal channels and efficient ball mapping is the spacing between the power supply and ground pins. Inserting too many serial RapidIO ports into a small package can cause signal integrity problems due to crosstalk, resulting in "closed eyes" as the signal travels from the switch to the endpoint.

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