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Focus on Signal Integrity in Complex Designs

Posted:05:35 PM December 12, 2018 writer: G

For the design of ASIC (Application Specific Integrated Circuit), the performance of standard cells is wasted due to the application of standard cells, shorter development cycle, and more relaxed protection between cells. Therefore, the key to high-end ASIC chip design is to ensure high-performance chips are delivered with shorter development time.

With the development of process technology, opportunities for signal crosstalk have increased. The number of metal wiring layers continues to increase: from 4 or 5 layers of the 0.35 um process to more than 7 metal wiring layers in the 0.13 um process. As the number of wiring layers increases, the adjacent channel capacitance also increases. In addition, the current increase in the number of circuit gates in complex designs has made more and longer interconnects necessary. The resistance on the long line increases, and the thinner and thinner metal lines also cause an increase in resistance due to the reduced cross-section of the interconnect. Even using the existing copper interconnect process does not solve this problem, just delaying the time to solve the resistance problem.

It is clear that the effects between these adjacent signal lines dominate the design decisions and require a more accurate model than in the past. The effect of one signal on another is related to the relative phase between the signals. For a phase-consistent signal, a victim network connected to a small receiver and transmitter on a 0.5 mm long signal line is accelerated by 30%. For a 1mm long signal line, the victim network is accelerated by 40%. For signals with opposite phases, the victim network connected to the small receiver and transmitter on the 0.5mm long signal line will decelerate by 70%, and when the signal line length is 1mm, the signal will decelerate by more than 100%.

One way to solve the signal crosstalk problem is to increase the spacing between the metal signal lines. By doubling the pitch of the signal lines, the signal crosstalk on the 0.5mm signal line can be reduced from 70% to 20%. The interference on the long signal line (1mm signal line) will also be reduced from 100% to 40%. However, crosstalk between signals still exists, and the method of reducing the crosstalk between signals by doubling the metal line pitch increases the chip area and increases the difficulty of wiring.

Take shielding measures

Another way to solve the above problem is to take shielding measures. By adding power or ground on both sides of the signal line, signal crosstalk is greatly reduced. Adding shielding to the system also requires good bypassing of all components and should ensure that the power and ground are as clean as possible. In fact, from an area point of view, this solution is worse than doubling the metal line spacing, because in this case the signal line spacing is 4 times the minimum line spacing, so this place The method of line spacing arrangement increases the complexity of the wiring by an order of magnitude.

However, the shielding method may be more suitable for some signal lines, for example, the clock line has a very high speed and the largest driver and buffer are connected to such a signal line. Phase-locked loop technology compensates for additional signal delays on the driver and buffer. Proper place and route ensures an isolated environment around the clock signal to minimize interference from the clock signal to the data signal.

In this approach, design engineers use extraction and analysis tools to detect areas that are prone to signal integrity problems, then select some of these areas and address this issue. If the problematic signal lines are isolated from each other, rewiring can solve the problem. A simpler approach is to change the drive size and add buffers to the victim network.

The logic synthesis process always selects the appropriate driver based on an approximate estimate of the online load. In general, logic synthesis always chooses a stronger driver to achieve excessive compensation of the expected load. However, the load is virtually unknown until the physical design is completed, and the actual load may vary from -70% to +200% compared to the expected load condition. The worst case scenario may be that an oversized drive on a short line is next to a long line with a very light load. One solution to the drive problem is to use a buffer to divide the long lines. This reduces the length of the line and the coupling capacitance, as well as reducing the load at the input of the buffer to the level of a single load. This technique ensures that minor changes in the buffer layout process ensure the implementation of the underlying planning and optimization. Adding a static timing analysis step to the design flow can handle noise and latency issues. The goal is to integrate the steps to resolve crosstalk and timing into one process. First, these tools extract parasitic parameters after placement and routing. Second, the signal delay is calculated based on the extracted load model without considering any crosstalk effects. These extracted delays are then labeled into the design and static timing analysis tools are used to determine incorrect timing. After getting the first approximation of the timing window, the design engineer adds the delay due to crosstalk and checks if the timing will exceed the assigned timing window. The complete design flow requires three static timing analyses.

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