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Electromagnetic compatibility design - circuit layout

Posted:04:19 PM December 27, 2018 writer: G

1. Ground layout

The ground wire is not only the potential reference point for the circuit operation, but also a low impedance circuit for the signal. The more common interference on the ground is the ground loop interference caused by the ground loop current. Solving this type of interference problem is equivalent to solving most of the electromagnetic compatibility problems. The noise on the ground line mainly affects the ground level of the digital circuit, while the digital circuit outputs a low level, which is more sensitive to ground noise. Interference on the ground line may not only cause malfunction of the circuit, but also cause conduction and radiation emission. Therefore, the focus of reducing these disturbances is to reduce the impedance of the ground as much as possible (for digital circuits, it is especially important to reduce the inductance of the ground).

Pay attention to the following points in the layout of the ground line:

(1) According to different power supply voltages, the digital circuit and the analog circuit respectively set the ground.

(2) The public ground line is as thick as possible. When using a multi-layer thick film process, the ground plane can be specifically set, which helps to reduce the loop area and also reduces the efficiency of receiving the antenna. And can be used as a shield for signal lines.

(3) Comb ground should be avoided. This structure makes the signal return loop large, which increases the radiation and sensitivity, and the common impedance between the chips may also cause the circuit to malfunction.

(4) When multiple chips are mounted on the board, a large potential difference will appear on the ground line. The ground line should be designed as a closed loop to improve the noise margin of the circuit.

(5) For boards with both analog and digital functions, the analog ground and digital ground are usually separated and connected only at the power supply.

2. The layout of the power cord

In general, electromagnetic interference caused by power lines is the most common, except for interference directly caused by electromagnetic radiation. Therefore, the layout of the power cord is also important, and the following rules should generally be observed.

(1) The power supply line is as close as possible to the ground line to reduce the power supply loop area, and the differential mode radiation is small, which helps to reduce circuit crosstalk. Do not overlap the power supply loops of different power supplies.

(2) When using a multi-layer process, the analog power supply and the digital power supply are separated to avoid mutual interference. Do not place the digital power supply on top of the analog power supply. Otherwise, a coupling capacitor will be generated to destroy the separation.

(3) The power plane and the ground plane can be completely dielectrically isolated. When the frequency and speed are high, a dielectric paste with a low dielectric constant should be used. The power plane should be close to the ground plane and arranged below the ground plane to shield the radiated current distributed in the power plane.

(4) Decoupling should be performed between the power supply pin and the ground pin of the chip. The decoupling capacitor uses a 0.01uF chip capacitor, which should be placed close to the chip to minimize the loop area of the decoupling capacitor.

(5) When using the chip chip, try to select the chip with the power pin and the ground pin close to each other, which can further reduce the power supply loop area of the decoupling capacitor, which is beneficial to achieve electromagnetic compatibility.

3. Signal line layout

When using a single-layer thin film process, a simple and convenient method is to lay the ground wire first, then arrange key signals, such as high-speed clock signals or sensitive circuits close to their ground loops, and finally route other circuits. The arrangement of the signal lines is preferably arranged in accordance with the flow direction of the signals, so that the signals on the circuit board are smooth.

If you want to minimize EMI, keep the signal line as close as possible to the reflow signal line that makes it as small as possible to avoid radiated interference. Low-level signal channels cannot be close to high-level signal channels and unfiltered power lines. Noise-sensitive wiring should not be parallel to high-current, high-speed switching lines. If possible, arrange all the key traces as strip lines. Incompatible signal lines (digital and analog, high speed and low speed, high current and low current, high voltage and low voltage, etc.) should be away from each other. Do not run in parallel. The crosstalk between signals is extremely sensitive to the length of adjacent parallel traces and the spacing of the traces, so try to make the high-speed signal line and other parallel signal lines widened and the parallel length is reduced.

The inductance of the conduction band is proportional to the logarithm of its length and length, and inversely proportional to the logarithm of its width. Therefore, the conduction band should be as short as possible, and the address lines or data lines of the same component should be kept as long as possible. The wires used as input and output of the circuit should avoid adjacent parallel as much as possible. It is better to add a grounding wire between them to effectively suppress crosstalk. The wiring density of low-speed signals can be relatively large, and the wiring density of high-speed signals should be as small as possible.

In the multi-layer thick film process, in addition to complying with the rules of single-layer wiring, you should also pay attention to:

Try to design a separate ground plane, and the signal layer is arranged adjacent to the ground plane. When not in use, a ground wire must be placed adjacent to the high frequency or sensitive circuitry. The signal lines distributed on different layers should be perpendicular to each other, which can reduce the electric field and magnetic field coupling interference between the lines; the signal lines on the same layer maintain a certain spacing, preferably separated by the corresponding ground line to reduce crosstalk between lines. Each high-speed signal line is limited to the same layer. Do not route the signal wire too close to the edge of the substrate. Otherwise, the characteristic impedance will change, and the fringe field will be easily generated to increase the outward radiation.

4. The layout of the clock line

Clock circuits play an important role in digital circuits and are the main source of electromagnetic radiation. A spectrum with a 2 ns rising edge radiates energy up to 160 MHz. Therefore, designing the clock circuit is the key to ensuring electromagnetic compatibility of the entire circuit. Regarding the layout of the clock circuit, there are the following considerations:

(1) Do not use a daisy-chain structure to transmit the clock signal. Instead, use a star structure, that is, all clock loads are directly connected to the clock power driver.

(2) All conduction bands connected to the crystal input/output terminals should be as short as possible to reduce noise interference and the effect of distributed capacitance on the crystal.

(3) The crystal capacitor ground wire should be connected to the device with the widest and shortest conduction band; the digital ground pin closest to the crystal should be minimized.

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