2. Confirm that the PCB template is up to date
3. Confirm that the template's positioning device is in the correct position
4. PCB design instructions and PCB design or change requirements, the standardization requirements are clear
5. Confirm that the layout on the outline drawing is prohibited and the wiring area has been reflected on the PCB template
6. Compare the outline drawing, confirm that the dimensions and tolerances marked on the PCB are correct, and the metalized holes and non-metalized holes are defined accurately.
7. Confirm the PCB template is correct, it is best to lock the structure of the file, in order to avoid misuse by the mobile location
8. Confirm that all device packages are consistent with the company's unified library and that the package libraries have been updated (check the run results with viewlog). If not, be sure to update the Symbols
9. Motherboard and daughter board, board and backplane, confirm the signal corresponding to the corresponding position, connector orientation and silk screen logo is correct, and the daughter board has anti-misinsertion measures, daughter board and the motherboard device should not interfere
10. Is the component placed 100%?
11. Open the place-bound of the TOP and BOTTOM layers of the device to see if DRC caused by overlap is allowed
12. Mark point is sufficient and necessary
13. heavier components, should be placed near the PCB support point or support edge to reduce the PCB warpage
14. Structure-related devices after the best layout of a good board lock to prevent misuse of the mobile location
15. Crimp socket around the range of 5mm, the front is not allowed to have height over the height of the crimp socket components, not allowed on the back of the components or solder joints
16. Confirm the device layout to meet the technological requirements (focus on BGA, PLCC, SMD socket)
17. Metal shell components, with special care not to collide with other components, to leave enough space position
18. Interface-related devices as close to the interface as possible, backplane bus driver placed as close to the backplane connector
19. Wave soldering surface CHIP device has been converted into a wave soldering package,
20. More than 50 hand-joints
21. Axially plug higher components on the PCB, horizontal mounting should be considered. Set aside lying space. And consider the fixed way, such as the fixed pad of the crystal
22. The need to use the heat sink devices, to confirm adequate spacing with other devices, and pay attention to the height of the main components within the heat sink range
23. digital-analog hybrid board digital circuit and analog circuit device layout has been separated, the signal flow is reasonable
24. The A / D converter is placed across the modulus partition.
25. Clock device layout is reasonable
26. High-speed signal device layout is reasonable
27. Terminating device has been placed (source matching string resistance should be placed on the signal driver side; the middle of the matching string resistance placed in the middle position; the terminal matching string resistance should be placed on the receiving end of the signal)
28. IC device decoupling capacitor number and location is reasonable
29. Signal lines with different levels of the plane as a reference plane, when crossing the plane of the partition area, the connection between the reference plane capacitance is close to the signal line area.
30. Protection circuit layout is reasonable, is conducive to segmentation
31. Is the board's power supply fuses near the connector without any circuit components in the front
32. Confirm strong signal and weak signal (power difference 30dB) circuit is laid out separately
33. Is placement of devices that could affect EMC experiments follow the design guidelines or reference to successful experience? Such as: panel reset circuit to be slightly close to the reset button
34. The heat-sensitive components (including liquid medium capacitance, crystal) as far as possible away from high-power components, heat sinks and other heat sources
35. Whether the layout to meet the thermal design requirements, cooling channels (according to the design process to implement the document)
36. Is the IC power too far from the IC
37. LDO and the surrounding circuit layout is reasonable
38 module power supply and other surrounding circuit layout is reasonable
39. The power of the overall layout is reasonable
40. Are all simulation constraints correctly added to Constraint Manager?
41. Is the correct set of physical and electrical rules (pay attention to the power network and network constraints set)
42. Test Via, Test Pin spacing settings are sufficient
43. Lamination thickness and program to meet the design and processing requirements
44. Have all the impedance characteristics of the differential line impedance has been calculated and used to control the rules
45. Digital circuits and analog circuits are separated tracks, the signal flow is reasonable
46. If the A / D, D / A, and similar circuits are divided, does the signal line between the circuits go from the bridge between the two places (with the exception of the differential line)?
47. The signal lines that must cross the gap between the split power supplies should refer to the complete ground plane.
48. If using stratigraphic design zoning is not divided, to ensure digital signal and analog signal zoning.
49. High-speed signal line impedance layers are consistent
50. High-speed differential signal lines and similar signal lines, whether the same length, symmetry, the nearest parallel lines?
51. Confirm that the clock line as far as possible in the inner
52. Confirm that the clock line, high speed line, reset line and other strong radiation or sensitive lines have been routed according to 3W principle
53. Clock, interrupt, reset signal, Fast / Gigabit Ethernet, high-speed signal whether there is no bifurcation test point?
54. LVDS and other low-level signals and TTL / CMOS signal is to try to meet the 10H (H for the signal line from the reference plane height)?
55. Whether the clock line and high-speed signal line to avoid the through-hole through the dense through-hole area or device pinout?
56. Whether the clock line has satisfied the requirement of (SI constraint) (whether the clock signal trace is less punctured, the trace is shorter, the reference plane is continuous, the main reference plane is GND as much as possible; if the layer is changed, the main reference plane of GND Layer, GND vias within 200 mils of vias) If the main reference plane of different levels is to be changed during layer change, is there a decoupling capacitor within 200 mils of the via hole?
57. differential pairs, high-speed signal lines, all kinds of BUS has fulfilled (SI constraints) requirements
58. For the crystal, whether it be distributed under the ground? Avoid signal lines from the device pin through between? For high-speed sensitive devices, to avoid the signal line from the device pin through between?
59. Board signal alignment can not have acute and right angles (generally a continuous turning angle of 135 degrees, the RF signal line is best to use arc-shaped or after the calculation of the cut angle copper foil)
60. For double-panel, check if the high-speed signal line is routed one next to the return ground; for multi-layer board, check if the high-speed signal line is as close as possible to the ground plane
61. For the adjacent two-layer signal traces, try to track vertically
62. Avoid signal lines from the power module, common mode inductors, transformers, filters under the cross
63. Try to avoid high-speed signals in the same layer of long-distance parallel routing
64. Board edges and digital ground, analog ground, the protection of the edge of the division whether there are additional shielding vias? Are multiple ground planes connected by vias? Is the via hole distance less than 1/20 of the wavelength of the highest frequency?
65 surge suppression device corresponding signal traces in the surface is short and thick?
66. Confirm the power, the formation of islands without isolation, no large slot, no due to the through-hole isolation disk is too large or dense hole caused by the long cracks in the ground plane, no slender and narrow channel phenomenon
67. Whether in the signal line across more layers, placed in the hole (at least two ground plane)
68. If the power / ground plane is divided, try to avoid the splitting of the reference plane with a high-speed signal across.
69. Confirm the power, can carry enough current. Whether the number of vias to meet the bearing requirements
70. For special requirements of the power supply, whether to meet the pressure drop requirements
71. In order to reduce the planar edge radiation effect, 20H principle should be satisfied as far as possible between the power plane and the ground plane. (If the conditions permit, the power layer indentation as much as possible).
72. If there is division, the division of the earth does not constitute a loop?
73. Adjacent layers of different power planes are avoided overlapping placement?
74. Protected ground, -48V ground and GND isolation is greater than 2mm?