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EMI Avoidance for 4-layer, 6-layer, 10-layer board

writer: G April 18, 2018

1. 4 layer board

There are several potential issues with 4-layer board design. First, a conventional four-layer board with a thickness of 62 mils, even if the signal layer is in the outer layer and the power and ground layers are in the inner layer, the spacing between the power layer and the ground layer is still too large.

If the cost requirement is first, consider the alternatives of the two traditional 4-layer boards below. Both of these solutions can improve EMI suppression performance, but are only suitable for applications where the density of the components on the board is low enough and there is sufficient area around the component (where the required power supply copper is placed).

The first is the preferred solution. The outer layers of the PCB are ground layers, and the middle two layers are signal/power layers. The power supply on the signal layer is wired with a wide wire, which makes the path impedance of the power supply current low, and the impedance of the signal microstrip path is also low. From the EMI control point of view, this is the best 4-layer PCB structure available.

The outer layer of the second scheme takes the power and ground, and the middle two layers take the signal. Compared with the traditional 4-layer board, this scheme has less improvement, and the inter-layer impedance is as poor as the traditional 4-layer board.

If you want to control the impedance of the traces, the above stacking scheme must be very careful to route the traces under the power and ground copper islands. In addition, copper islands on the power supply or ground should be interconnected as much as possible to ensure DC and low frequency connectivity.

2. 6-layer board

If the density of the components on the 4-layer board is relatively large, it is preferable to use a 6-layer board. However, some laminate schemes in 6-layer board designs do not provide good shielding of electromagnetic fields and have little effect on the transient signal reduction of power busbars. Two examples are discussed below:

The first example places the power supply and ground on the 2nd and 5th layers respectively. Because of the high impedance of the copper coating on the power supply, it is very unfavorable to control common mode EMI radiation. However, from the perspective of signal impedance control, this method is very correct.

The second example places the power supply and ground on the 3rd and 4th layers respectively. This design solves the problem of copper resistance of the power supply. Due to poor electromagnetic shielding performance of the 1st and 6th layers, differential mode EMI increases. If the number of signal lines on the two outer layers is the smallest and the trace length is short (less than 1/20 of the highest harmonic wavelength of the signal), this design can solve the problem of differential mode EMI. Copper-filled non-element and non-lead areas on the outer layer and grounding of the copper area (every 1/20 wavelength interval) are particularly good at suppressing differential mode EMI. As mentioned earlier, the copper area is to be connected to the internal ground plane at multiple points.

The general purpose high-performance 6-layer board design generally lays layers 1 and 6 as ground, and layers 3 and 4 take power and ground. Since there are two layers of dual microstrip signal lines centered between the power plane and the ground plane, the EMI suppression capability is excellent. The disadvantage of this design is that there are only two layers in the trace layer. As mentioned earlier, if the outer traces are short and copper is not routed in the trace area, the same stacking can be achieved using a conventional 6-layer board.

Another 6-layer board layout is signal, ground, signal, power, ground, and signal, which can achieve the environment needed for advanced signal integrity design. The signal layer is adjacent to the ground plane and the power plane is paired with the ground plane. Obviously, the disadvantage is that the layer stack is not balanced.

This usually causes troubles for processing and manufacturing. The solution to the problem is to fill all the blank areas of the third layer with copper. If the copper density of the third layer is close to the power layer or the ground layer after the copper is filled, the board may not be counted as a structurally balanced circuit board. . The copper fill area must be connected to power or ground. The distance between the connected vias is still 1/20 wavelength, not necessarily all the way to connect, but ideally it should be connected.

3. 10-layer board

Since the insulating layer between the multilayer boards is very thin, the impedance between the 10 or 12 layers of the circuit board layers is very low. As long as there is no problem with delamination and stacking, excellent signal integrity is entirely expected. It is difficult to manufacture 12-layer boards with a thickness of 62mil, and there are not many manufacturers capable of processing 12-layer boards.

Since the signal layer and the loop layer are always separated by an insulating layer, the scheme of distributing the middle 6 layers to design the signal line in the 10-layer board design is not optimal. In addition, it is important that the signal layer and the loop layer are adjacent, that is, the board layout is signal, ground, signal, signal, power, ground, signal, signal, ground, and signal.

This design provides a good path for the signal current and its loop current. The appropriate routing strategy is to route layer 1 in the X direction, layer 3 in the Y direction, layer 4 in the X direction, and so on. Intuitively looking at the line, Layer 1 and Layer 3 are a paired layered combination, Layers 4 and 7 are a paired layered combination, Layers 8 and 10 are the last paired layered combination. When you need to change the direction of the trace, the signal line on the first layer should change direction after passing through the "via" to the third layer. In fact, it may not always be possible to do so, but as a design concept, it is still necessary to comply with it.

Similarly, when the signal's trace direction changes, it should be via vias from the 8th and 10th layers or from the 4th layer to the 7th layer. This routing ensures the tightest coupling between the signal's forward path and the loop. For example, if the signal is routed on layer 1 and the loop is routed on layer 2 and only on layer 2, then even if the signal on layer 1 goes to layer 3 by “via,” it The loop is still on the second layer, maintaining low inductance, large capacitance characteristics, and good electromagnetic shielding performance.

If the actual alignment is not the case, what should I do? For example, the signal line on the first layer goes through the via to the 10th layer. At this time, the loop signal has to find the ground plane from the 9th layer. The loop current must find the nearest ground via (such as the ground pin of the resistor or capacitor). . If it happens that there are such holes in the vicinity, it is really lucky. If no such vias are available, the inductance will increase, the capacitance will decrease, and the EMI will increase.

When the signal line must leave the current pair of wiring layers through the vias to other wiring layers, ground vias should be placed next to the vias so that the loop signals can be smoothly returned to the proper ground plane. For Layer 4 and Layer 7 layer combinations, the signal loop will return from either the power plane or the ground plane (ie, the 5th or 6th layer) because the capacitive coupling between the power plane and the ground plane is good and the signal is easily transmitted.


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