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Signal Integrity is a state in which the signal is not damaged. It shows that the signal maintains its correct functional characteristics after transmission through the signal line. The signal can respond with correct timing and voltage in the circuit. It can be known from the timing of the IC if the signal is in steady state time (in order to correctly identify and process the data, The IC requires a large transition within the time period during which the input data remains unchanged before and after the clock edge, and the IC may misjudge or lose part of the data. If the signal has good signal integrity, the circuit has the correct timing relationship and signal amplitude, and the data will not be captured by mistake, which means that the receiver can obtain relatively pure data. Conversely, if a signal integrity fault such as false triggering, damped oscillation, overshoot, undershoot occurs, any signal transition will occur, causing the input distortion data to be sent into the latch or captured on the distorted clock edge. Data, the signal can not respond properly, resulting in abnormal system operation and performance degradation.
The earlier the signal integrity (SI) problem is solved, the more efficient the design is, so that the termination of the device is not added until the board design is complete. There are many tools and resources for SI design planning. This article explores the core issues of signal integrity and several methods for solving SI problems, ignoring the technical details of the design process.
Signal integrity issues have different ways of expressing them. The timing problem is always the first, and the shortening of the signal rise time and fall time will first cause timing problems in the designed system. Secondly, signal oscillation, signal overshoot and undershoot due to transmission line effects can pose a great threat to the fault tolerance and monotonicity of the design system. In slow systems, interconnect delays and signal oscillations are often overlooked by design engineers, primarily because signal sway caused by transmission line effects has sufficient time to stabilize in slow systems. However, as signal transitions continue to increase and system clock frequencies continue to increase, the time it takes for signals to travel between devices and prepare for clock timing is greatly reduced. The severity of the problem has suddenly increased and the likelihood of failure has increased rapidly.
Regarding signal integrity issues, when the system clock exceeds 50 MHz, the signal interconnect on the board introduces signal delays on the timing path, and these signal delays constrain the performance of the board-level design. How the transmission line effect will quickly introduce serious signal integrity issues like signal oscillation, overshoot and undershoot, and how these issues will threaten the noise tolerance of the design and the monotonic consistency principle of the design.
Such as skin effect and dielectric loss, effects of vias and connectors, differential signaling and routing considerations, power distribution and EMI control.
This article focuses on some of the signal integrity issues that PCB design needs to consider in gigabit device data transfers.
Many people are very vague about the concept of the critical length of the lines on the PCB. Even many people don't even know the concept. If you design a high-speed circuit board but don't know the concept, you can be sure that the final board may not work stably. And you are confused, you can't start debugging.
The rise time of the signal is critical to understanding the signal integrity problem. Most of the problems in high-speed pcb design are related to it, and you must pay enough attention to him.
Today's computer system DDR3 memory technology has been widely used, and the data transmission rate has been repeatedly improved, and has now reached 1866Mbps. Under such high-speed bus conditions, to ensure the reliability of data transmission quality and meet the timing requirements of parallel buses, it poses great challenges to design implementation.
To maintain signal integrity on printed circuit boards, a unique approach to inter-layer interconnects (vias) that allows the trace impedance to be accurately matched should be used.
With the increase of package density and the increase of operating frequency, the signal integrity problem in MCM circuit design can not be ignored. Taking the detector circuit as an example, this paper firstly uses APD software to realize the layout and layout design of the circuit, and then combines the signal integrity analysis to adjust the circuit layout and wiring structure repeatedly. The final Spectra Quest software simulation results show that the improved circuit layout and routing Meet signal integrity requirements while maintaining high simulation accuracy.
Due to the time relationship, this paper only explains the operation steps. The application needs to have a deeper operational capability and signal integrity theory foundation for protel99se and a certain understanding of the constrained drive design method of modern EDA software. As for why I would consider protel99se for signal integrity analysis, because of the company's reasons, the company originally wanted to cadence, but since I came to the company, the board with experience has been able to pass, there is nothing to change the design. The problem of the tool, the company is not familiar with cadence in order to take care of other people, so I don't think about it anymore. Although I know that there is no need for cadence when the requirements are high, I have no choice but to repeatedly replace the design tools. I have to make an idea on protel99se. This is The origin of this article.
More and more manufacturers are requesting the DC trace impedance on the PCB. The reasons for specifying and controlling the DC trace impedance are given below from the designer's point of view.
As the current demand for speed and bandwidth for communications and computer systems continues to rise, system designers are facing a severe test. The parallel bus structure tested in time series is close to the limit of its capability, and the bus width is now over 64 bits, which makes the circuit layout extremely complicated. In addition, the large number of signals in a wide parallel bus are also very cumbersome to synchronize, especially as these signals are subject to random factors such as noise and crosstalk.
In order to perform circuit simulation, it is necessary to first build a model of the component, that is, for the various components supported by the circuit simulation program, there must be a corresponding mathematical model to describe them in the simulation program, that is, a calculation formula that can be calculated by a computer. To express them.
IBIS is the abbreviation of I/OBufferInformationSpecification. It is a fast and accurate method for I/OBUFFER based on I/V curve. It is an international standard that reflects the electrical characteristics of chip driver and receiver. It provides a standard file. The format is used to record parameters such as drive source output impedance, rise/fall time, and input load. It is ideal for calculation and simulation in high-speed circuit design such as oscillation and crosstalk.
Common PCB board level signal integrity analysis model
Knowing the basic principles of the IBIS model, it is easy to perform signal integrity analysis on the designed circuit. Due to the high precision and transparency of the IBIS model, it was supported by major EDA vendors as soon as it was introduced. Now all kinds of EDA tools have the function of system simulation using IBIS model, and some of them integrate with PCB design tools. In the design process, the simulation of signals can be directly performed online, which is very convenient to use.
With the advancement of technology, the signal blocking time of high-speed integrated circuits has reached several hundred ps, and the clock frequency can reach several hundred MHz. Such a high edge rate causes a large number of interconnect lines on the printed circuit board to be produced in low-speed circuits. The transmission line effect causes distortion of the signal, which seriously affects the correct transmission of the signal. If the board design is not considered, the circuit with the correct logic function will not work properly when debugging. In order to solve this problem, signal integrity analysis must be carried out when designing high-speed circuits. The system is thoroughly simulated by virtual template, and the influence of circuit layout and routing on signal integrity is accurately analyzed, and the circuit design is guided. In this way, many problems that can be found in debugging can be solved during the design, which greatly improves the design success rate and shortens the design cycle.
As the packing density increases and the operating frequency increases, the signal integrity problem in MCM circuit design cannot be ignored. Taking the detector circuit as an example, this paper firstly uses APD software to realize the layout and layout design of the circuit, and then combines the signal integrity analysis to adjust the circuit layout and wiring structure repeatedly. The final Spectra Quest software simulation results show that the improved circuit layout and routing Meet signal integrity requirements while maintaining high simulation accuracy.