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What is the reduction in noise and electromagnetic interference in PCB design?
Posted: 03:22 PM March 05, 2019 Updated: 03:22 PM March 05, 2019

(1) High-speed chips can be used in low-speed chips without using high-speed chips.

(2) The method of string resistance can be used to reduce the jump rate of the upper and lower edges of the control circuit.

(3) Try to provide some form of damping for relays and the like.

(4) Use the lowest frequency clock that meets the system requirements.

(5) The clock generator is as close as possible to the device using the clock. The quartz crystal oscillator housing should be grounded.

(6) Circle the clock area with the ground wire and keep the clock line as short as possible.

(7) The I/O driver circuit should be as close as possible to the edge of the printed board, so that it can leave the printed board as soon as possible. The signal entering the printed board should be filtered, and the signal from the high-noise area should be filtered. At the same time, the signal of the string termination is used to reduce the signal reflection.

(8) The useless end of the MCD should be connected to the ground, or grounded, or defined as the output end. The end of the integrated circuit should be connected to the ground of the power supply. Do not hang it.

(9) Do not leave the input terminal of the unused circuit. The unused input terminal is grounded, and the negative input terminal is connected to the output terminal.

(10) Printed boards should use 45-fold lines instead of 90-fold lines to reduce the external transmission and coupling of high-frequency signals.

(11) The printed board is divided according to the frequency and current switching characteristics, and the noise component is farther away from the non-noise component.

(12) Single-panel and double-panel single-point power supply and single-point grounding, power supply line and grounding wire are as thick as possible. If the economy can withstand, use multi-layer board to reduce the power supply and grounding inductance.

(13) The clock, bus, and chip select signals should be kept away from the I/O lines and connectors.

(14) The analog voltage input line and reference voltage terminal should be as far as possible from the digital circuit signal line, especially the clock.

(15) For A/D type devices, the digital part and the analog part are more uniform and do not cross.

(16) The clock line is perpendicular to the I/O line and has less interference than the parallel I/O line. The clock component pins are far from the I/O cable.

(17) The component pins are as short as possible, and the decoupling capacitor pins are as short as possible.

(18) The key lines should be as thick as possible and with protective ground on both sides. The high speed line should be short and straight.

(19) Noise-sensitive lines should not be parallel to high current, high-speed switching lines.

(20) Do not route underneath the quartz crystal and below the noise sensitive device.

(21) Weak signal circuit, do not form a current loop around the low frequency circuit.

(22) Do not form a loop in the signal. If it is unavoidable, make the loop area as small as possible.

(23) One decoupling capacitor per integrated circuit. A small high frequency bypass capacitor is added to each electrolytic capacitor.

(24) Use a large-capacity tantalum capacitor or a condenser capacitor instead of an electrolytic capacitor for the circuit to charge and discharge the storage capacitor. When using a tubular capacitor, the housing should be grounded.

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