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Use of high speed PCB vias
Posted: 02:12 PM February 27, 2019 Updated: 02:12 PM February 27, 2019

1. Parasitic capacitance

The via itself has a parasitic capacitance to ground or power. If the via is known to have a diameter of D2 on the inner layer; the diameter of the via pad is D1; the thickness of the PCB is T; The electrical constant is ε;

The parasitic capacitance of the via delays the rise of the signal in the circuit, reducing the speed of the circuit. If a PCB with a thickness of 25 mils uses a via with an inner diameter of 10 mils and a pad diameter of 20 mils and an inner gap width of 32 mils, the parasitic capacitance of the vias can be approximated by the above formula to be approximately 0.259 pF. If the characteristic impedance of the trace is 30 Ω, the rise time of the signal caused by the parasitic capacitance is increased. The factor 1/2 is because the via is in the middle of the trace. It can be seen from these values that although the effect of the rising edge caused by the parasitic capacitance of a single via is not obvious, if the via is used multiple times in the trace for interlayer switching, the designer must carefully consider it.

2. Parasitic inductance

Vias also have series parasitic inductances that are directly related to their height and diameter. If nine is the height of the via; d is the diameter of the center hole; then the parasitic inductance L of the via is approximately

In the design of high-speed digital circuits, the parasitic inductance brings more harm than the parasitic capacitance. The parasitic series inductance of the vias weakens the bypass capacitor's filtering noise at the power or ground plane, reducing the filtering effect of the entire power system. Therefore, the vias of the bypass and decoupling capacitors should be as short as possible to make them inductive. The smallest.

Through the analysis of the parasitic characteristics of the vias above, in order to reduce the adverse effects of the parasitic effects of the vias, the high-speed PCB design should be done as follows:

· Minimize vias, especially clock signal traces;

· Using a thinner PCB helps to reduce the two parasitic parameters of the via;

· The via impedance should match the impedance of the connected trace as much as possible to reduce the reflection of the signal;

· Choose a reasonable via size. For multilayer, dense-density PCBs, vias of 0.25 mm / 0.51 mm / 0.91 mm (drilled diameter / pad diameter / inner isolation area diameter) are preferred; for some high-density PCBs, 0.20 can be used. For vias of mm/0.46 mm/0.86 mm, non-through vias can also be tried; for vias of power or ground, larger sizes can be considered to reduce impedance;

· The inner layer of the electrical isolation zone is as large as possible. Considering the density of the via holes on the PCB, it generally satisfies D2=Dg+0.41 mm;

• The power and “ground” pins should be placed close to the vias. The shorter the leads between the vias and pins, the better, as they result in an increase in inductance. At the same time, the power and ground leads should be as thick as possible to reduce the impedance;

• Place some ground vias near the vias of the signal-changing layer to provide a short-distance loop for the signal.

In design, we should consider both cost and signal quality. In high-speed PCB design, we hope that the smaller the via, the better, so that there is more wiring space on the board. In addition, the smaller the via, the parasitic capacitance. The smaller, the more suitable for high speed circuits. Therefore, balanced design should be given to the design of vias for high-speed PCBs.

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