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The Latest Application of Protel99se Signal Integrity
Posted:10:02 AM November 20, 2018 writer: G

1. Set the mapping type of passive devices R, C, and L under menu preferences.

2. Set the layer thickness and copper thickness in LAYER STACK MANANGER.

3. Set the required SI rules in DESIGN/DESIGN RULES/SIGNAL INTEGRITY.

4. Run TOOLS/SIGNAL INTEGRITY, run import IBIS-FILE in the signal integrity interface, and import the IBIS model file of the analysis chip.

5. The most critical step, edit the Design Explorer 99 with a text editor

SE\Library\SignalIntegrity\User\u_parts.hrt, this file specifies all available device models for PROTEL99SE, in ASCII format, which is easy to understand, where you can create new device models and introduce each device for each new device. The pin specifies the pin macro model imported in step 4. It can be specific to each pin and change the device name to COMMENT (of course you can also change COMMENT) in the PCB.

The following is a simple device format:

TI!SN74221N PQ[16] TYP["DIC"]

IN[1--3,9--11]("TTL_000_S0_in.mac"),

[6,7,14,15]

OUT[4,5,12,13]("TTL_000_S0_out.mac")

BI[6,7,14,15]

VCC[16]

GND[8]

6. Return to the PCB interface of protel99se and run Reports/SIGNAL INTEGRITY. If the ICs with valid models column in the report identifies the model of the device model you edited earlier, the setup is complete, you can return to DESIGN/DESIGN RULES/ SIGNAL INTEGRITY sets the signal integrity rules in detail and checks them with tools/design rules check. Similarly, in the signal integrity interface after running TOOLS/SIGNAL INTEGRITY, there is no need to set the pin model of the signals one by one, which is already based on u_parts. The settings in the hrt file are automatically recognized, and the signals can be directly selected for analysis.

Advantages: The buffer model can be specific to the pin. The batch signal analysis result is much more accurate than the default model. It can do accurate batch analysis of overshoot and undershoot in reflection analysis. It can also be more accurate in the signal integrity interface. A single crosstalk analysis and Fourier-expanded frequency domain analysis that determines the harmful EMI harmonic components of the signal.

Disadvantages: The model of the exclusion is still unrecognizable, and the simulation will not work when there is an exclusion of passive components. Due to the lack of understanding of the calculation method of delay time, the current constraints on timing are currently not possible.

  • PCB
    Portotype
  • PCB
    Assembly
  • SMD
    Stencil

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