Signal Integrity Design for Gigabit Device PCBs

The rapid development of communication and computer technology has enabled high-speed PCB design to enter the gigabit field. New high-speed device applications enable such long-distance transmission over long distances on backplanes and boards, but at the same time, PCB design Problems with signal integrity issues (SI), power integrity, and electromagnetic compatibility are also more prominent. Signal integrity refers to the quality of the signal transmitted on the signal line. The main problems include reflection, oscillation, timing, ground bounce and crosstalk. Poor signal integrity is not caused by a single factor, but by a combination of factors in the board design. In a PCB design for gigabit devices, a good signal integrity design requires engineers to fully consider device, transmission line interconnect schemes, power distribution, and EMC issues. High-speed PCB design EDA tools have evolved from simple simulation verification to design and verification, helping designers set rules early in the design process to avoid errors rather than identifying problems later in the design process. As data rates become more complex and more complex, high-speed PCB system analysis tools become more necessary, including timing analysis, signal integrity analysis, design space parameter scanning analysis, EMC design, power system stability analysis, etc. .

High speed device and device model

Although Gigabit transmit and receive component suppliers will provide design information about the chip, there is a process for the device vendor to understand the signal integrity of the new device, so the design guidelines given by the device vendor may not be mature. It is often the design constraints imposed by the device vendor that are often very demanding, and it can be very difficult for a design engineer to meet all of the design rules. Therefore, signal integrity engineers need to use simulation analysis tools to analyze the constraints and actual design of suppliers, and to examine and optimize component selection, topology, matching schemes, matching component values, and ultimately develop signal integrity. PCB layout rules. Therefore, accurate simulation analysis of gigabit signals becomes very important, and the role of device models in signal integrity analysis is gaining more and more attention.

Component models typically include the IBIS model and the Spice model. Since the board-level simulation only cares about the signal response of the output pin through the interconnect system to the input pin, and the IC manufacturer does not want to leak detailed circuit information inside the device, and the transistor-level Spice model simulation time is usually unbearable, the IBIS model is on the high-speed PCB. The design field is increasingly accepted by more and more device manufacturers and signal integrity engineers.

For the simulation of Gigabit device PCB systems, engineers often question the accuracy of the IBIS model. When the device is operating in the saturation and cut-off regions of the transistor, the IBIS model lacks sufficient detailed information to describe that in the nonlinear region of the transient response, the results simulated with the IBIS model do not produce accurate response information like the transistor-level model. However, for ECL type devices, the IBIS model which is in good agreement with the transistor-level model simulation results can be obtained. The reason is very simple. The ECL driver works in the linear region of the transistor, and the output waveform is closer to the ideal waveform. It can be accurately obtained according to the IBIS standard. The IBIS model.

As data transmission rates increase, differential devices developed on the basis of ECL technology have been greatly developed. The LVDS standard and CML make Gigabit signal transmission possible. From the above discussion, the IBIS standard is still applicable to the design of gigabit systems due to the circuit structure and the corresponding differential technology applications. The published application of some IBIS models in 2.5Gbps LVDS and CML design also proves this.

Since the IBIS model is not suitable for describing active circuits, the IBIS model is not suitable for many Gbps devices with loss compensation for pre-emphasis circuits. Therefore, in gigabit system design, the IBIS model can only work effectively under the following conditions:

1. Differential device operates in the amplification region (linear V-I curve)

2. The device does not have an active pre-emphasis circuit

3. The device has a pre-emphasis circuit but does not start up (starting the pre-emphasis function under a short interconnect system may result in worse results)

4. The device has a passive pre-emphasis circuit, but the circuit can be separated from the die of the device.

When the data rate is 10 Gbps or more, the output waveform is more like a sine wave, and the Spice model is more suitable.