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Discussion on EMI Avoidance Techniques
Posted: 04:50 PM April 18, 2018 Updated: 04:50 PM April 18, 2018

1. Power bus

Properly placing a capacitor of appropriate capacity near the IC's power supply pins allows the IC's output voltage to jump faster. Because of the finite frequency response of the capacitor, this makes it impossible for the capacitor to generate the full harmonic power required to cleanly drive the IC output. In addition, transient voltages formed on the power busbars create a voltage drop across the inductance of the decoupling path. These transient voltages are the main source of common-mode EMI interference.

In the case of an IC on a circuit board, the power plane surrounding the IC can be seen as an excellent high-frequency capacitor that collects the energy leaked by discrete capacitors that provide high-frequency energy for clean output. In addition, the inductance of the excellent power layer is small, so that the transient signal synthesized by the inductor is also small, thereby reducing common-mode EMI.

The connection from the power plane to the IC power pin must be as short as possible because the rising edge of the digital signal is getting faster and faster. It is best to connect directly to the pad where the IC power pin is located.

To control common-mode EMI, the power plane must be conducive to decoupling and have a sufficiently low inductance. This power plane must be a pair of well-designed power planes. So, what kind of degree is it? The answer depends on the layering of the power supply, the material between the layers, and the operating frequency (as a function of IC rise time). Typically, the power layered spacing is 6 mils and the interlayer is FR4 material. The equivalent capacitance per square inch power plane is approximately 75 pF. Obviously, the smaller the interlayer spacing, the greater the capacitance.

According to the current speed of development of ICs, devices with a rise time in the range of 100 to 300 ps will occupy a very high proportion. For circuits with rise times of 100 to 300ps, the 3-mil spacing will no longer apply for most applications. At that time, it was necessary to use a layering technique with an interlayer spacing of less than 1 mil and to replace the FR4 dielectric material with a material with a high dielectric constant. Ceramic and ceramic plastics can now meet the design requirements for 100 to 300ps rise time circuits.

For today's common 1 to 3 ns rise time circuits, 3 to 6 mil spacing, and FR4 dielectric materials, high-end harmonics can often be handled and transients can be low enough, that is, common-mode EMI can be reduced. The PCB layered stack design example given in this article will assume a 3 to 6 mil spacing between layers.

2. Electromagnetic shielding

From the perspective of signal traces, a good slicing strategy should be to put all the signal traces in one or several layers, which are next to the power plane or ground plane. For power supplies, a good tiering strategy should be that the power plane is adjacent to the ground plane and the distance between the power plane and the ground plane is as small as possible.

3. PCB stacking

What kind of stacking strategy helps shield and suppress EMI? The following layered stacking scheme assumes that the supply current flows on a single layer, with single or multiple voltages distributed in different parts of the same layer.

4. Design of multiple power planes

If two power planes of the same voltage source need to output large currents, the circuit board should be laid out into two sets of power and ground planes. In this case, insulation is placed between each pair of power and ground planes. This results in two equal pairs of equal-impedance busbars for our desired bisecting current. If the stacking of the power planes causes unequal impedances, the shunting will be uneven, the transient voltage will be much larger, and the EMI will increase dramatically.

If there are multiple supply voltages with different values on the board, multiple power planes are required accordingly, keeping in mind that different power planes and ground planes are created for different power supplies. In both cases, when determining the location of the paired power plane and ground plane on the board, keep in mind the manufacturer's requirements for the balancing structure.

Sum up

Thickness, via process, and circuit board layer count are not critical to the board design. A good layered stack ensures that the power bus is bypassed and decoupled, minimizing the transient voltage on the power plane or ground plane. The key to shielding the signals from the electromagnetic field of the power supply. Ideally, there should be an insulating isolation layer between the signal trace layer and the loop ground layer. The smaller the pair spacing (or more than one pair) should be, the better. Based on these basic concepts and principles, you can design a circuit board that can always meet the design requirements.

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