Signal Integrity Solutions
For chip design, there are usually two ways to solve signal integrity problems. The RF solution focuses on the transmission line, often using impedance matching on the package boundary, while the digital (ie, broadband) solution emphasizes the choice of package, controlling the number of simultaneous switching and switching speed, and using between the external power supply pins of the package and ground. Bypass capacitors, the capacitance inside the IC is achieved by the overlap of the metal layers, which provides a local low-impedance path for high-speed transient currents to prevent ground bounce.
However, when faced with signal integrity issues in deep sub-micron designs, the usual solution no longer applies. For example, limiting the edge rate (Slew rate) can significantly improve ground bounce and crosstalk, but it also limits the clock rate. Researching new solutions must be able to accommodate deep submicron IC designs. For example, increasing substrate resistance can be solved by silicon-on-insulator (SOI), a technology widely used in micro-IC designs. Now, the main methods to solve the signal integrity problem are circuit design, reasonable layout and modeling and simulation.
1. Circuit design
In the circuit design process, the number of outputs is synchronously controlled by design control, and the maximum edge rate (dI/dt and dV/dt) of each unit is controlled to obtain the lowest and acceptable edge rate, which can effectively control signal integrity. . Differential signals can also be selected for high output function blocks such as clock drivers. For example, the clock typically uses an ECL signal or a full swing differential signal. For application engineers, passive components (resistors, capacitors, and ferrites) are typically terminated on the transmission line to achieve impedance matching between the transmission line and the load. The choice of termination strategy should be a compromise between increasing component count, switching speed, and power consumption. Terminating the series resistor R or RC circuit should be as close as possible to the excitation or receiver, and obtain impedance matching. At the same time, the resistor R (such as 10Ω) can consume the useless DC power of the logic circuit. The capacitor (such as 39PF) can meet the switch. The damping oscillation strength is weakened under the condition of speed, but at the same time, the capacitor must be carefully selected to prevent ringing caused by its lead inductance.
2. Reasonable wiring
Wiring is very important. Designers should use existing design experience, integrate multiple possible solutions, optimize wiring, and eliminate potential problems without violating general principles. While there are some rule-driven routers that help designers optimize their designs, there is no router that is completely customizable by the user and fully supports signal integrity analysis. The routing tool should be combined with all parasitic extraction to obtain accurate predictions of time lag and latency. Successful routers should not only have accurate parasitic extraction, but also be combined with signal integrity tools to cut wires and reroute when signal integrity is found to fall below the required threshold.
3. Modeling simulation
Properly performing circuit modeling and simulation is the most common solution. In modern high-speed circuit design, simulation analysis shows its superiority. It gives the designer accurate and intuitive design results, which facilitates early detection of hidden dangers, timely modification, shortened design time and reduced design cost. The designer should make reasonable estimates of relevant factors and establish a reasonable model. For IC design, the simulation of the circuit must be carried out in a packaged environment, and the simulation results can be closer to the silicon test results returned after the mold is molded. Since signal integrity issues often occur as intermittent errors, emphasis is placed on synchronous switching control, simulation, and packaging to ensure that the design meets signal integrity requirements and solves problems before wafer fabrication. For IC applications, simulation can be used to select reasonable termination components and optimize the layout of components, making it easier to identify potential problems and take correct termination strategies and layout constraints to resolve related signal integrity issues. As clock frequencies increase and IC size continues to decrease, maintaining signal integrity is becoming more challenging for designers, making modeling simulation an integral part of design.