The increase in semiconductor complexity and the total number of logic gates has required integrated circuits to have more pins and finer pin pitch. Designing a 2000+ pin on a 1mm pitch BGA device is now commonplace, not to mention placing 296 pins on a device with a 0.65mm pin pitch. Faster rise times and signal integrity (SI) requirements require a greater number of power and ground pins, and therefore require more layers in the multilayer board, which drives higher micro vias The need for density interconnect (HDI) technology.
HDI is an interconnect technology that is being developed in response to these needs. Micro-vias and ultra-thin dielectrics, finer traces, and smaller line spacing are key features of HDI technology.
2. RF design
For RF designs, the RF circuit should be designed directly into the system schematic and system board layout and not used in a separate environment for subsequent conversions. All of the simulation, tuning, and optimization capabilities of the RF simulation environment are still necessary, but the simulation environment accepts more primitive data than the "real" design. Therefore, the differences between the data models and the resulting design changes will disappear. First, designers can directly interact between system design and RF simulation. Second, if designers do a large-scale or reasonably complex RF design, they may want to assign circuit simulation tasks to multiple computing platforms running in parallel, or They want to send each circuit in a design that consists of multiple modules to their respective simulators, thereby reducing the simulation time.
3. Improve the packaging of seniors
The increasing functional complexity of modern products requires a corresponding increase in the number of passive components, which is mainly reflected in the increase in the number of decoupling capacitors and termination resistors in low-power, high-frequency applications. Although the packaging of passive surface-mount devices has been reduced to considerable size after several years, the results are still the same when trying to achieve the maximum limit density. Printed component technology enables the transition from multi-chip modules (MCMs) and hybrid components to SiPs and PCBs that can be used directly as embedded passives today. In the process of transformation, the latest assembly technology was used. For example, the inclusion of an impedance material layer in a layered structure and the use of series termination resistors directly under the microball grid array (uBGA) package have greatly improved the circuit's performance. Embedded passive components now have a high-precision design, eliminating the need for additional processing steps for laser cleaning welds. Wireless components are also moving in the direction of increasing integration directly within the substrate.
4. Rigid flexible PCB
In order to design a rigid flexible PCB, all factors that affect the assembly process must be considered. Designers cannot simply design a rigid flexible PCB as if designing a rigid PCB as if the rigid flexible PCB were another rigid PCB. They must govern the bending area of the design to ensure that the design points will not cause the conductor to break and peel due to the stress of the curved surface. There are still many mechanical factors to consider, such as minimum bend radius, dielectric thickness and type, sheet metal weight, copper plating, overall circuit thickness, number of layers, and number of bends.
Understand rigid flex design and decide if your product promises you to create a rigid flexible design.
5. Signal integrity planning
In recent years, new technologies related to parallel bus structures and differential pair structures for serial-to-parallel conversion or serial interconnection have been continuously improved.
Figure 2 shows the typical design issues encountered for a parallel bus and serial-to-parallel conversion design. The limitation of parallel bus design is the change of system timing, such as clock skew and propagation delay. Because of the clock skew on the entire bus width, the design of the timing constraints is still a problem. Increasing the clock rate only makes the subject worse.
On the other hand, the differential pair structure uses a swappable point-to-point connection at the hardware level for serial communication. Typically, it transfers data through a unidirectional serial "channel" that can be stacked into 1-, 2-, 4-, 8-, 16-, and 32-wide configurations. Each channel carries one byte of data, so the bus can handle data widths from 8 bytes to 256 bytes and maintain data integrity by using some form of error detection technique. However, because of the high data rate, other design issues have arisen. The clock recovery at high frequencies becomes a burden on the system, because the clock must quickly lock the input data stream, and to reduce the jitter during all cycle-to-week periods in order to improve the debouncing function of the circuit. Power noise also poses additional problems for designers. This type of noise increases the potential for severe jitter, which can make eye opening more difficult. Another challenge is to reduce common-mode noise and solve problems caused by loss effects from IC packages, PCBs, cables, and connectors.
6. Practicality of Design Suite
Design kits such as USB, DDR/DDR2, PCI-X, PCI-Express, and RocketIO will undoubtedly greatly assist designers in their entry into new technologies. The Design Suite gives an overview of the technology, specific instructions, and the challenges the designer will face, followed closely by simulations and how to create routing constraints. It provides documentation along with the program, which provides the designer with an opportunity to grasp the advanced technology of the older generation.
It seems easy to get a PCB tool that can handle layouts; but getting a tool that can not only meet the layout but also solve your immediate needs is crucial.