1. From the perspective of function, the vias can be divided into two categories.
One is used as an electrical connection between the layers; the other is used for the fixing or positioning of the device.
In terms of process process, these vias are generally divided into three categories, namely, blind vias, buried vias, and through vias.
The blind vias are located on the top and bottom surfaces of the printed wiring board and have a depth for the connection of the surface wiring to the underlying inner wiring. The depth of the holes usually does not exceed a certain ratio (aperture).
Buried hole refers to a connection hole located in the inner layer of the printed wiring board, which does not extend to the surface of the circuit board. The above two types of holes are located in the inner layer of the circuit board, and are completed by a through hole forming process before lamination, and several inner layers may be overlapped during the formation of the via holes.
The third type is called a through hole, and the hole passes through the entire circuit board and can be used to implement internal interconnection or as a mounting hole for the component. Since the vias are easier to implement in the process and lower in cost, most printed circuit boards use it without the need for two other vias. The via holes described below are considered as through holes unless otherwise specified.
From a design point of view, a via is mainly composed of two parts, one is a drill hole in the middle, and the other is a pad area around the hole. The size of these two parts determines the size of the vias. Obviously, in highspeed, highdensity PCB design, the designer always hopes that the smaller the via, the better, so that more wiring space can be left on the board. In addition, the smaller the via, the parasitic capacitance of its own. The smaller, the more suitable for high speed circuits. However, the reduction in the size of the hole also brings about an increase in cost, and the size of the via hole cannot be reduced indefinitely. It is limited by the process techniques such as drilling and plating: the smaller the hole, the smaller the drill The longer the hole takes, the easier it is to deviate from the center position; and when the depth of the hole exceeds 6 times the diameter of the hole, there is no guarantee that the hole wall can be uniformly plated with copper. For example, the thickness of a normal 6layer PCB (throughhole depth) is about 50Mil, so PCB manufacturers can provide a minimum diameter of 8Mil.
2. Via parasitic capacitance
The via hole itself has a parasitic capacitance to the ground. If the via hole diameter of the via hole on the ground layer is known to be D2, the diameter of the via pad is D1, the thickness of the PCB board is T, and the dielectric constant of the board substrate is ε, the parasitic capacitance of the via is similar to: C=1.41εTD1/(D2D1) The parasitic capacitance of the via will have a major effect on the circuit by prolonging the rise time of the signal and reducing the speed of the circuit.
For example, for a PCB with a thickness of 50Mil, if a via with an inner diameter of 10Mil and a pad diameter of 20Mil is used, and the distance between the pad and the ground copper area is 32Mil, the via hole can be approximated by the above formula. The parasitic capacitance is roughly: C=1.41x4.4x0.050x0.020/(0.0320.020)=0.517pF, and the amount of rise time caused by this part of capacitance is: T1090=2.2C(Z0/2)=2.2x0 .517x(55/2)=31.28ps . It can be seen from these values that although the effect of the rise and delay caused by the parasitic capacitance of a single via is not obvious, if the vias are used multiple times in the trace for interlayer switching, the designer must carefully consider it.
3. Parasitic inductance of vias
Similarly, there are parasitic inductances in the vias where parasitic capacitances exist. In the design of highspeed digital circuits, the parasitic inductance of vias often causes more damage than parasitic capacitance. Its parasitic series inductance weakens the contribution of the bypass capacitor and reduces the filtering effectiveness of the entire power system.
We can simply calculate the parasitic inductance of a via approximation using the following formula: L = 5.08h [ln(4h/d)+1] where L is the inductance of the via, h is the length of the via, and d is the center The diameter of the hole. It can be seen from the equation that the diameter of the via has less influence on the inductance, and the greatest influence on the inductance is the length of the via.
Still using the above example, the inductance of the via can be calculated as: L = 5.08 x 0.050 [ln (4x0.050 / 0.010) + 1] = 1.015nH. If the rise time of the signal is 1 ns, then the equivalent impedance is: XL = πL / T10  90 = 3.19 Ω. Such an impedance cannot be ignored in the presence of highfrequency current. It is important to note that the bypass capacitor needs to pass through two vias when connecting the power plane to the ground plane, so that the parasitic inductance of the via is multiplied.
4. Via design in high speed PCB
Through the above analysis of the parasitic characteristics of vias, we can see that in highspeed PCB design, seemingly simple vias often have a large negative effect on the design of the circuit. In order to reduce the adverse effects of the parasitic effects of vias, it is possible to do as much as possible in the design:
1. From the perspective of cost and signal quality, choose a reasonable size of the via size. For example, for 610 layer memory module PCB design, 10/20Mil (drill/pad) vias are better. For some highdensity smallsize boards, you can also try 8/18Mil. hole. Under current technical conditions, it is difficult to use smaller size vias. For vias for power or ground, consider using larger sizes to reduce impedance.
2. The two formulas discussed above can be concluded that using a thinner PCB board helps to reduce the two parasitic parameters of the via.
3. The signal traces on the PCB should not be changed as much as possible, that is, try not to use unnecessary vias.
4. The power and ground pins should be punched in the vicinity, and the shorter the leads between the vias and pins, the better, because they lead to an increase in inductance. At the same time, the power and ground leads should be as thick as possible to reduce the impedance.
5. Place some grounded vias near the vias of the signalchanging layer to provide the most recent loop for the signal. It is even possible to place a large number of redundant ground vias on the PCB.
Of course, you need to be flexible in design. The via model discussed above is where each layer has pads, and sometimes we can reduce or even remove pads from certain layers. Especially in the case of very large via density, it may cause a broken channel in the copper layer to form a partition circuit. To solve such a problem, in addition to moving the position of the via, we can also consider the via in the copper layer. The pad size is reduced.
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