PCB design skills based on GENESIS2000 software (2)

writer: G May 06, 2019

6. Circuit layer production

6.1 Off-board graphics deletion

a. Select all the board layers except the rout layer, and select the outline frame one by one in the panel and delete it;

b. Use the Clip Area function, parameter Method select profile, parameter Clip area select outside, automatically delete the off-board graphics;

c. Check and remove the unfinished graphics on the edge of the board.

6.2 Pick the surface sticker

a. Select the component surface circuit layer, open the Feature selection filter function in the panel, select smd in Attributes and press select to select all surface stickers on the component surface layer;

b. Paste all the surface of the component surface circuit layer to the new layer gtl and check whether the number of remaining pads on the component surface wiring layer is equal to the number of holes. If the quantity is equal, it proves that the surface label attribute is completely defined. If it is not equal, you need to find the pad with no surface label attribute defined. Select Edit→attributes→Chang function, select smd in attributes, and then press OK to manually define the remaining surface stickers. And move to the gtl layer;

c. Move all the graphics of the gtl layer back to the component surface circuit layer. If you need to compensate the SMD, you can increase it as required while moving.

d. Select all surface stickers of the component surface layer and add 11mil to the new layer D10.

e. Find the identification point in the D10 layer r-shaped D code, determine the position of the identification point, add the copper ring to the identification point of the component layer circuit board edge, the outer diameter of the copper ring is larger than the inner diameter by 1mm, and the inner diameter ratio is the resistance point of the identification point. Large 1mm, can not touch the surrounding graphics;

f. The welding surface circuit layer is fabricated as above.

6.3 line width compensation

a. Select all the line layers, open the Feature selection filter function in the panel, close the Pads, Surfaces, Text and Negative elements buttons, press select to select all the lines to be compensated, and then use the Edit→Resize→Global function to increase. For impedance control lines, separate compensation is performed according to impedance requirements.

6.4 disk alignment

Select all the board layers, use the DFM→Pad Snapping function to align the reference layer of each layer of the pad, and the offset will not move above 2mil, so the producer needs to raise it.

6.5 Line Layer Hole Pad Optimization

a. Select the component-side circuit layer and use the DFM→Signal Layer Opt function to optimize the pad by default parameters. Check the optimization results, such as the ARG violation (min) report, indicating that the pads are not optimized due to insufficient spacing. First undo this optimization step, then open the column chart to see if the aperture of the unoptimized pad belongs to Via or Plt, then reduce the corresponding welding ring parameters of the hole step by step with 0.5mil, and re-optimize until the optimization is completed. Maintain existing parameters to optimize the welding surface layer;

b. The inner pad optimization method is the same as the outer layer;

c. Move the component plane layer hole pad to the gtl layer, change the gtl layer attribute to board+ signal+ positive, re-optimize the gtl layer pad with the DFM→Signal Layer Opt function, and maintain the original settings for the parameters PTH AR and VIA AR. , the parameters Spacing and Drill to cu are changed to 0. After the optimization is completed, all the graphics in the gtl layer are moved back to the component plane layer. This step is also repeated for the weld face.

Note: All outer layers use the same optimization parameters, all inner layers also use the same optimization parameters, and the outer and inner parameters can be different.

6. No function pad removal

a. Use the DFM→NFP Removal function to automatically remove the inner unwired pad; turn off the PTH and Via options in the parameter Drill, and change the parameter Remove undrilled Pads to No to automatically remove the outer NPTH pad;

The welding surface D11 is made in the same way, and the layer name is jobs-a.d11.

7. Solder mask

a. Select the component surface layer, use DFM→Solder Mask Opt function for resistance welding optimization, ERF parameter select SHENNAN-E80, Clearance Opt parameter setting see b;

b. The solder mask opening window should be as large as possible under the condition of the spacing (except for single-side solder mask opening ≥3mil, copper foil thickness ≥3OZ). This solves the problem of alignment of the field board and the problem of the pad on the ink.

The specific manufacturing method and steps of the CAM board: the selection of the solder mask optimization parameters is determined according to the minimum spacing of the line at the window of the pad. The GENESIS 2000 CAM software we use now, solder masking can only be optimized by one value. Solder mask optimization parameter clearance (min) + coverage(min) = spacing(min) , where clearance : pad solder mask opening; coverage: window to line distance; spacing: minimum spacing of the line. The selection method of the solder mask optimization parameters is: when the line spacing is ≥ 4 mil, clearance (min) à 2.5 mil; clearance (opt) à 3.0 mil (depending on the spacing can be ≥ 3 mil defaults to 3 mil); coverage (min) à 1. 5mil; coverage(opt) à 1.5mil. In this way, the place where the spacing between the plates is large can be 3 mils, and the place with smaller spacing cannot reach 3 mils and is made by 2.5 mils.

c. Simultaneously open the pattern before and after optimization of the surface solder mask, and the visual inspection has no obvious size and shape change;

d. Use Analysis→Fabrication→Solder Mask Checks function to analyze whether the optimized component surface soldering meets the requirements. If it does not meet the requirements, it should be manually adjusted until the analysis is qualified.

e. Select layer 1, use Actions→reference Selection function to select gts layer to select, parameter Mode select Disjoint, close lines, Surfaces, Text, Arcs&Circles button, select the hole of the solderless unopened window and copy it to a new layer of tmp. In tmp, the aperture is changed to the finished aperture and then moved to the component surface solder mask to remove the tmp layer;

f. moving the Pads in the gts layer back to the component surface solder mask;

g. Move the Lines in the gts layer back to the component surface solder mask;

h. Check the number of pads on the component surface solder mask equal to the number of pads on the component surface circuit layer + the number of NPTH holes;

i. Solder mask solder mask is made in the same way.

8. BGA plug hole

a. Copy the BGA pads of the component plane layer and the solder plane layer to a new layer of 2mm;

b. Change all the pad sizes in the 2mm layer to s4000μm, and fill in the blank space in the middle of the block;

c. Select the drilling layer, use the Actions→reference Selection function to select the 2mm layer to select, the parameter Mode selects Touch, copy all the holes that touch the 2mm layer (ie the holes in the BGA2mm range) to Job.bga, and copy Job.bga is Job.sdb;

d. Change the aperture in Job.bga (plug template) and Job.sdb (plug hole plate);

e. Select the D11 layer, use the Actions→reference Selection function to select the Job.bga layer to select, the parameter Mode selects Touch, delete all the pads that touch the Job.bga layer, and the number of deletions should be the same as the number of plug holes;

f. Select the solder mask, open the Feature selection filter function in the panel, select the large solder pad and the small window pad in the solder mask layer and the finished hole in the Include Symbols, and use the Actions→reference Selection function to refer to the Job.bga layer. Select, the parameter Mode selects Touch, and the pad that touches the Job.bga layer is deleted.

9. Network comparison

a. Open the Actions→Netlist Analyzer function, Step selects orig and edit respectively, Type selects current, press Recalc button respectively;

b. After Recalc is completed, change the previous current to Reference, press Update, and pop up the Ref Netlist Update dialog box. Select Set to CUR netlist in the Action and press OK.

c. Press compare to compare the network relationship between orig and edit. If the shorted and broken are not red, the result is correct.

10. Character layer

A. Modify the character line width;

b. Select the mark in the Special symbols according to the customer's request, the mark should be added in the blank, and the solder resistance, shape and copper on the line surface should not be touched;

c. Production D10;

d. Copy the D10 layer to the corresponding character layer, and Invert select No.

  • PCB
  • SMT
  • Stencil






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