PCB process skills based on GENESIS2000 software (2)

writer: G April 04, 2019

4. Drilling editing

1. Drilling production steps

a. Open the Drill Tools Manager and check whether the hole diameter, hole number and hole properties in the drilling file are correct according to the drill pattern provided by the customer. If there is no drilling pattern, the drilling file shall prevail;

b. Change the via property with small aperture and irregular distribution from plt to via;

c. Enter the hole diameter corresponding to each hole according to the Drilling Tool Compensation Rules.

d. Analyze the drilled layer with Analysis→Fabrication→Drill Checks function to check whether the analysis result is abnormal;

e. If there are heavy holes, use NFP Removal function, parameter Delete to select Duplicate, automatically remove the drilling hole and the heavy plate of the corresponding layer;

f. If there are intersecting holes, manually delete the smaller vias in the cross holes and the corresponding pads of each layer; if the device holes are crossed, they cannot be deleted, and two pre-drills that are tangent to the intersecting holes should be added at both ends of the intersecting holes. Hole, theoretically pre-drilled hole diameter = (cross hole center distance + cross hole hole diameter) / 2, and then use the tail method to select the hole diameter (in principle, the hole diameter is already selected in the plate). For example, the two cross holes have a hole diameter of 2.15 mm and a center distance of 1.00 mm. When the hole diameter is calculated to be 1.575 mm, the pre-drill hole diameter is 1.55 mm.

2. Drilling slot 

a. In the drilling layer, change the shape of the required drill slot to oval with the Edit→Reshape→Change Symbol command. The drill slot is 3.00X1.00 and the shape is oval3X1.

b. Interrupt the oval with the Edit→Reshape→Break command into line;

c. If the required length to width ratio of the drill slot is <2, add two pre-drilled holes at both ends of the slot, in the same way as the intersecting holes.

5. Drilling outline drawing


a. Copy the rout layer to the new layer tmp with the Edit→Copy→Other Layer command, and increase the 5mil;

b. In the tmp layer, use the Add feature function to mark the complete and correct dimensions. The line width and dimension line width is r5mil, the arrow uses special symbol→jian/jian45, and the size value is Text.

The parameters are XY 80 mils and the line width is 5 mils;

c. Use the Creat Drill Map function to automatically generate the drilling pattern, the unit is set to mm, and the drilling pattern is named map;

d. Move all the graphics in the tmp layer to the map layer, and the description text in the customer drilling diagram is also moved to the map layer and merged into a drilled outline drawing;

e. Remove the tmp layer.

6. Circuit layer

1. Off-board graphics deletion

a. Select all the board layers except the rout layer, select the outline frame one by one in the panel and delete


b. Use the Clip Area function, parameter Method select profile, parameter Clip area select outside, automatically delete the off-board graphics;

c. Check and remove the unfinished graphics on the edge of the board.

2. Pick the surface sticker

a. Select the component surface circuit layer, open the Feature selection filter function in the panel, select smd in Attributes and press select to select all surface stickers on the component surface layer;

b. Paste all the surface of the component surface circuit layer to the new layer gtl and check whether the number of remaining pads on the component surface wiring layer is equal to the number of holes. If the quantity is equal, it proves that the surface label attribute is completely defined. If it is not equal, you need to find the pad that defines the surface label property. Select Edit→attributes→Chang function, select smd in attributes, and then press OK to manually define the remaining surface. Paste and move to the gtl layer;

c. Move all the graphics of the gtl layer back to the component surface circuit layer. If you need to compensate the SMD, you can increase it as required while moving.

d. Select all surface stickers of the component surface layer to add 11mil to copy to the new layer D10

e. Find the identification point in the D10 layer r-shaped D code, determine the position of the identification point, add the copper ring to the identification point of the component layer board layer edge, the outer diameter of the copper ring is larger than the inner diameter by 1mm, and the inner diameter ratio is the resistance point of the identification point. Large 1mm, can not touch the surrounding graphics;

f. The welding surface circuit layer is fabricated as above.

3. Line width compensation

a. Select all the line layers, open the Feature selection filter function in the panel, close the Pads, Surfaces, Text and Negative elements buttons, press select to select all the lines to be compensated, and then use the Edit→Resize→Global function to increase. For the increased value, see b for the impedance control line and compensate separately for the impedance requirement.

4. Disk alignment

Select all the board layers, use the DFM→Pad Snapping function to align the pad reference layer of each layer, and the offset will not move above 2mil.

5. Line layer hole pad optimization

a. Select the component-side circuit layer and use the DFM→Signal Layer Opt function to optimize the pad by default parameters. Check the optimization results, such as the ARG violation (min) report, indicating that the pads are not optimized due to insufficient spacing. First undo this optimization step, then open the column chart to see if the aperture of the unoptimized pad belongs to Via or Plt, then reduce the corresponding welding ring parameters of the hole step by step with 0.5mil, and re-optimize until the optimization is completed. Maintain existing parameters to optimize the welding surface layer;

b. The inner pad optimization method is the same as the outer layer;

c. Move the component plane layer hole pad to the gtl layer, change the gtl layer attribute to board+ signal+ positive, re-optimize the gtl layer pad with the DFM→Signal Layer Opt function, and maintain the original settings for the parameters PTH AR and VIA AR. , the parameters Spacing and Drill to cu are changed to 0. After the optimization is completed, all the graphics in the gtl layer are moved back to the component plane layer. This step is also repeated for the weld face.

Note: All outer layers use the same optimization parameters, all inner layers also use the same optimization parameters, and the outer and inner parameters can be different.

6. No function pad removal

a. Use the DFM→NFP Removal function to automatically remove the inner unwired pad; turn off the PTH and Via options in the parameter Drill, and change the parameter Remove undrilled Pads to No to automatically remove the outer NPTH pad;

f. The welding surface D11 is made in the same way, and the layer name is jobs-a.d11.

  • PCB
  • SMT
  • Stencil






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