How to enhance anti-static ESD function when designing PCB

writer: G April 25, 2018

Electrostatic discharges from the human body, the environment, and even electronic equipment can cause various damages to precision semiconductor chips, such as penetrating the thin insulation layer inside components; damaging the gates of MOSFETs and CMOS components; and trigger locking in CMOS devices. Short-circuit reverse-biased PN junction; short-circuit forward-biased PN junction; melting of the active device's internal solder or aluminum wire. In order to eliminate the electrostatic discharge (ESD) interference and damage to electronic devices, a variety of technical measures need to be taken to prevent them.

In the design of the PCB, the anti-ESD design of the PCB can be achieved through layering, proper layout and installation. In the design process, most of the design modifications can be limited to increasing or decreasing components through prediction. By adjusting the PCB layout, ESD can be well guarded. Here are some common precautions.

Use multi-layer PCBs wherever possible. Compared to double-sided PCBs, the ground plane and power plane, and the tightly spaced signal line-to-ground spacing can reduce the common-mode impedance and inductive coupling to 1/1 of a double-sided PCB. 10 to 1/100. Try to place each signal layer close to a power or ground plane. There are components for the top and bottom surfaces, with very short connections

Lines and many high density PCBs filled with ground can be considered for inner layer lines.

For double-sided PCBs, tightly interwoven power and ground grids are used. The power cord is close to the ground and should be connected as much as possible between the vertical and horizontal lines or the fill area. The grid size on one side is less than 60mm, if possible, the grid size should be less than 13mm.

Make sure each circuit is as compact as possible.

As far as possible, put all connectors aside.

If possible, introduce the power cord from the center of the card and away from areas that are susceptible to ESD directly.

Place a wide chassis or polygonal footprint on all PCB layers under the connector leading to the outside of the chassis (which is easily hit directly by the ESD), and connect them together with vias approximately every 13mm. Place mounting holes on the edges of the card, and solder-free top and bottom solder pads are connected around the mounting holes to the chassis ground.

Do not apply any solder to the top or bottom pads during PCB assembly. Use screws with built-in washers to achieve close contact between the PCB and the metal chassis/shield or bracket on the ground plane.

The same "isolation zone" should be set between the chassis ground and the circuit ground in each floor; if possible, keep the separation distance at 0.64mm.

At the top and bottom of the card, close to the mounting holes, connect the chassis ground and the circuit ground with a 1.27mm wide line every 100mm along the chassis ground. Adjacent to these connection points, pads or mounting holes for mounting are placed between the chassis ground and the circuit ground. These ground connections can be cut with a blade to keep the circuit open, or jumper with magnetic beads/high frequency capacitors.

If the circuit board is not placed in a metal chassis or shield, solder paste should not be applied on the top and bottom chassis grounds of the board so they can be used as discharge electrodes for ESD arcs.

To set a ring around the circuit in the following way:

(1) In addition to the edge connector and the chassis ground, an annular ground path is placed around the entire periphery.

(2) Make sure that the annular width of all layers is greater than 2.5mm.

(3) Rings are connected at intervals of 13mm.

(4) Connect the ring ground to the common ground of the multilayer circuit.

(5) For double panels installed in a metal chassis or shielding device, the ring should be connected to the circuit in a common way.

An unshielded double-sided circuit should be ring-shaped and connected to the chassis ground. The ring ground must not be coated with a solder mask so that the ring can act as a discharge pin for ESD. At least one is placed at a location on the ring (all layers). A 0.5mm wide gap avoids the formation of a large loop. The distance of the signal wiring from the ring ground can not be less than 0.5mm.